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Sat, 23 Sep 2023 11:26:10 +0000 Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 38NBQ9jl015317 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sat, 23 Sep 2023 11:26:09 GMT Received: from [10.253.9.19] (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.30; Sat, 23 Sep 2023 04:26:05 -0700 Message-ID: <164945f5-dde9-bfe7-80f4-9ae6736a6259@quicinc.com> Date: Sat, 23 Sep 2023 19:26:03 +0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.15.1 Subject: Re: [PATCH v6 4/4] clk: qcom: add clock controller driver for qca8386/qca8084 To: Stephen Boyd , , , , , , , , , , CC: , , , , References: <20230901091823.30242-1-quic_luoj@quicinc.com> <20230901091823.30242-5-quic_luoj@quicinc.com> <27ae3297ad161fd67706db70b402db04.sboyd@kernel.org> <16d09acf-7bdd-04ee-6faf-936c0366df03@quicinc.com> <17681a9f756cc70a190c674c51b90140.sboyd@kernel.org> <5a4805f7-f802-b1ba-9804-59c0fe6c7f26@quicinc.com> <92058c25fb11b75ee0a2298a684825e9.sboyd@kernel.org> <82adb75659e0d278e25b65b0e81df99a.sboyd@kernel.org> <9952fa20-a27f-3240-cc49-5c5109febfc1@quicinc.com> <580f3934ab1171e27d785db7362c342d.sboyd@kernel.org> Content-Language: en-US From: Jie Luo In-Reply-To: <580f3934ab1171e27d785db7362c342d.sboyd@kernel.org> Content-Type: text/plain; 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Sat, 23 Sep 2023 04:26:36 -0700 (PDT) On 9/15/2023 12:30 AM, Stephen Boyd wrote: > Quoting Jie Luo (2023-09-12 20:27:25) >> >> >> On 9/13/2023 1:18 AM, Stephen Boyd wrote: >>> Quoting Jie Luo (2023-09-12 05:07:02) >>>> >>>> and freq_tbl are necessary to this clock. >>> >>> I still don't see why the freq_tbl is necessary. >> >> Hi Stephen, >> For clk_rcg2_ops, freq_tbl is used to find the closest rate to decided >> the parent clock, the configuration of clock source and clock divider >> are saved in the freq_tbl to configure the RCG hardware register, the >> mapping of parent clock and hardware register value is decided by the >> freq_tbl for the RCG clock. > > The divider is always 1. The frequency is the frequency of the parent. > The two pieces of information are already known without the frequency > table. Why is it needed? Hi Stephen, i uploaded the new patchset V9 to remove these redundant freq_tbl by using the clk_ops clk_ops clk_rcg2_mux_closest_ops, thanks for this suggestion for the code improvement. Best Regards, Jie