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Date:   Sat, 23 Sep 2023 15:03:14 -0700
From:   Dan Williams <dan.j.williams@intel.com>
To:     <torvalds@linux-foundation.org>
CC:     <linux-cxl@vger.kernel.org>, <linux-kernel@vger.kernel.org>
Subject: [GIT PULL] Compute Express Link (CXL) Fixes for 6.6-rc3
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Hi Linus, please pull from:

  git://git.kernel.org/pub/scm/linux/kernel/git/cxl/cxl tags/cxl-fixes-6.6-rc3

...to receive a collection of regression fixes, bug fixes, and some
small cleanups.

The regressions arrived in the v6.5 dev cycle and missed the v6.6 merge
window due to my personal absences this cycle. The most important fixes
are for scenarios where the CXL subsystem fails to parse valid region
configurations established by platform firmware. This is important
because agreement between OS and BIOS on the CXL configuration is
fundamental to implementing "OS native" error handling, i.e. address
translation and component failure identification.

Other important fixes are a driver load error when the BIOS lets the
Linux PCI core handle AER events, but not CXL memory errors.

The other fixes in this pull might have end user impact, but for now are
only known to trigger in our test/emulation environment.

Bjorn, has acked the PCI core touches. This has all appeared in -next,
and now I see that 5 days ago Stephen noticed that a Fixes tag has the
wrong format:

  Fixes: ("27b3f8d13830 cxl/region: Program target lists")

  vs:

  Fixes: 27b3f8d13830 ("cxl/region: Program target lists")

...I decided against a late rebase for that. Please pull, or otherwise
let me know if you want the rebase.

---

The following changes since commit 0bb80ecc33a8fb5a682236443c1e740d5c917d1d:

  Linux 6.6-rc1 (2023-09-10 16:28:41 -0700)

are available in the Git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/cxl/cxl tags/cxl-fixes-6.6-rc3

for you to fetch changes up to c66650d29764e228eba40b7a59fdb70fa6567daa:

  cxl/acpi: Annotate struct cxl_cxims_data with __counted_by (2023-09-22 14:31:04 -0700)

----------------------------------------------------------------
cxl fixes for v6.6-rc3

- Fix multiple scenarios where platform firmware defined regions fail to
  be assembled by the CXL core.

- Fix a spurious driver-load failure on platforms that enable OS native
  AER, but not OS native CXL error handling.

- Fix a regression detecting "poison" commands when "security" commands
  are also defined.

- Fix a cxl_test regression with the move to centralize CXL port
  register enumeration in the CXL core.

- Miscellaneous small fixes and cleanups

----------------------------------------------------------------
Alison Schofield (2):
      cxl/region: Match auto-discovered region decoders by HPA range
      cxl/region: Refactor granularity select in cxl_port_setup_targets()

Dan Williams (1):
      cxl/port: Fix cxl_test register enumeration regression

Ira Weiny (1):
      cxl/mbox: Fix CEL logic for poison and security commands

Kees Cook (1):
      cxl/acpi: Annotate struct cxl_cxims_data with __counted_by

Smita Koralahalli (3):
      cxl/pci: Fix appropriate checking for _OSC while handling CXL RAS registers
      PCI/AER: Export pcie_aer_is_native()
      cxl/pci: Replace host_bridge->native_aer with pcie_aer_is_native()

 drivers/cxl/acpi.c         |  4 ++--
 drivers/cxl/core/mbox.c    | 23 ++++++++++++-----------
 drivers/cxl/core/port.c    | 13 +++++++++----
 drivers/cxl/core/region.c  | 41 +++++++++++++++++++++++++++++++----------
 drivers/cxl/pci.c          |  7 +++----
 drivers/pci/pcie/aer.c     |  1 +
 drivers/pci/pcie/portdrv.h |  2 --
 include/linux/aer.h        |  2 ++
 8 files changed, 60 insertions(+), 33 deletions(-)