Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:2 as permitted sender) client-ip=2620:137:e000::3:2;
MIME-Version: 1.0
References: <20230918123355.262115-1-biju.das.jz@bp.renesas.com>
 <20230918123355.262115-3-biju.das.jz@bp.renesas.com> <CACRpkdYYKAFLvpKH0ih5qZVbv7L3auny5WWx+qKa_HD1o-vsog@mail.gmail.com>
 <OS0PR01MB5922A256D2C57963ADEBCEDB86F9A@OS0PR01MB5922.jpnprd01.prod.outlook.com>
 <CACRpkdbM+XNjvxBZQFzZCsU+3V7PucBhbi_WjVtnGpakFQasAw@mail.gmail.com> <OS0PR01MB592202B4523DDC18B3E4511D86F9A@OS0PR01MB5922.jpnprd01.prod.outlook.com>
In-Reply-To: <OS0PR01MB592202B4523DDC18B3E4511D86F9A@OS0PR01MB5922.jpnprd01.prod.outlook.com>
From:   Linus Walleij <linus.walleij@linaro.org>
Date:   Mon, 25 Sep 2023 15:19:32 +0200
Message-ID: <CACRpkdYXXWVemZ0TBKN46rTTO4yChLjfsKioNm-HSZrNKQZDZw@mail.gmail.com>
Subject: Re: [PATCH 2/2] pinctrl: renesas: rzg2l: Enable noise filter for GPIO
 interrupt input
To:     Biju Das <biju.das.jz@bp.renesas.com>
Cc:     Geert Uytterhoeven <geert+renesas@glider.be>,
        Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>,
        Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>,
        Marc Zyngier <maz@kernel.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        "linux-renesas-soc@vger.kernel.org" 
        <linux-renesas-soc@vger.kernel.org>,
        "linux-gpio@vger.kernel.org" <linux-gpio@vger.kernel.org>,
        Biju Das <biju.das.au@gmail.com>
Content-Type: text/plain; charset="UTF-8"
Content-Transfer-Encoding: quoted-printable
Precedence: bulk

On Wed, Sep 20, 2023 at 4:06=E2=80=AFPM Biju Das <biju.das.jz@bp.renesas.co=
m> wrote:

> > > 2) Digital Noise Filter Clock Selection Register (FILCLKSEL):
> > >
> > > The FILCLKSEL register selects the divided clock to be input to digit=
al
> > noise filters.
> > >
> > > 00b: Not divided (initial value)
> > > 01b: Divided by 9000 (41.666 ns x 9000 =3D 375,000 ns)
> > > 10b: Divided by 18000 (41.666 ns x 18000 =3D 750,000 ns)
> > > 11b: Divided by 36000 (41.666 ns x 36000 =3D 1,500,000 ns)
> > > Note: This value is the value when the external clock is 24MHz.
> > >
> > > Q1) What is the recommended way to associate the above values with
> > >     PIN_CONFIG_INPUT_DEBOUNCE?
> > >
> > > Eg: I need to configure filter on, 8 stage filter , a divisor of 1800=
0
> > for a mechanical button bounce noise.
> >
> > As per the generic pin config and DT bindings:
> >
> >  * @PIN_CONFIG_INPUT_DEBOUNCE: this will configure the pin to debounce
> > mode,
> >  *      which means it will wait for signals to settle when reading inp=
uts.
> > The
> >  *      argument gives the debounce time in usecs. Setting the
> >  *      argument to zero turns debouncing off.
> >
> >   input-debounce:
> >     $ref: /schemas/types.yaml#/definitions/uint32
> >     description: Takes the debounce time in usec as argument or 0 to
> > disable
> >       debouncing
> >
> > The recommended way is to pass the desired clock cycle in microseconds =
as
> > the argument to the pin config.
>
> How to add number of FF stages info on top of this clock cycle?

You don't, look below.

> Use some encoding in DT and decode it in driver??

No you put in the desired delay in microseconds, the  you use
the table that you already provided to look up the appropriate
divisor:

> 00b: Not divided (initial value)
> 01b: Divided by 9000 (41.666 ns x 9000 =3D 375,000 ns)
> 10b: Divided by 18000 (41.666 ns x 18000 =3D 750,000 ns)
> 11b: Divided by 36000 (41.666 ns x 36000 =3D 1,500,000 ns)

For 0, 375, 750 and 1500 us...

> Note: This value is the value when the external clock is 24MHz.

And this can be provided from the clock framework, and then
you need some more elaborate math to calculate the right
divisor from the parameter in the device tree.

Yours,
Linus Walleij