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Mon, 25 Sep 2023 07:14:36 -0700 (PDT) Message-ID: <3ad5d3e4-dee1-74b5-6bb2-4a4fa3d2e071@tuxon.dev> Date: Mon, 25 Sep 2023 17:14:34 +0300 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.15.1 Subject: Re: [PATCH v5 3/8] drm: atmel-hlcdc: add LCD controller layer definition for sam9x75 Content-Language: en-US To: Manikandan Muralidharan , sam@ravnborg.org, bbrezillon@kernel.org, airlied@gmail.com, daniel@ffwll.ch, nicolas.ferre@microchip.com, alexandre.belloni@bootlin.com, lee@kernel.org, dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Hari.PrasathGE@microchip.com, Balamanikandan.Gunasundar@microchip.com, Durai.ManickamKR@microchip.com, Nayabbasha.Sayed@microchip.com, Dharma.B@microchip.com, Varshini.Rajendran@microchip.com, Balakrishnan.S@microchip.com References: <20230915104849.187146-1-manikandan.m@microchip.com> <20230915104849.187146-4-manikandan.m@microchip.com> From: claudiu beznea In-Reply-To: <20230915104849.187146-4-manikandan.m@microchip.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Spam-Status: No, score=-3.6 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,NICE_REPLY_A,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (howler.vger.email [0.0.0.0]); Mon, 25 Sep 2023 07:14:44 -0700 (PDT) On 15.09.2023 13:48, Manikandan Muralidharan wrote: > Add the LCD controller layer definition and descriptor structure for > sam9x75 for the following layers, s/,/: > - Base Layer > - Overlay1 Layer > - Overlay2 Layer > - High End Overlay > > Signed-off-by: Manikandan Muralidharan > --- > drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c | 97 ++++++++++++++++++++ > 1 file changed, 97 insertions(+) > > diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c > index fa0f9a93d50d..d30aec174aa2 100644 > --- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c > +++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c > @@ -462,6 +462,99 @@ static const struct atmel_hlcdc_dc_desc atmel_hlcdc_dc_sam9x60 = { > .layers = atmel_hlcdc_sam9x60_layers, > }; > > +static const struct atmel_hlcdc_layer_desc atmel_xlcdc_sam9x75_layers[] = { > + { > + .name = "base", > + .formats = &atmel_hlcdc_plane_rgb_formats, > + .regs_offset = 0x60, > + .id = 0, > + .type = ATMEL_HLCDC_BASE_LAYER, > + .cfgs_offset = 0x1c, > + .layout = { > + .xstride = { 2 }, > + .default_color = 3, > + .general_config = 4, > + .disc_pos = 5, > + .disc_size = 6, > + }, > + .clut_offset = 0x700, > + }, > + { > + .name = "overlay1", > + .formats = &atmel_hlcdc_plane_rgb_formats, > + .regs_offset = 0x160, > + .id = 1, > + .type = ATMEL_HLCDC_OVERLAY_LAYER, > + .cfgs_offset = 0x1c, > + .layout = { > + .pos = 2, > + .size = 3, > + .xstride = { 4 }, > + .pstride = { 5 }, > + .default_color = 6, > + .chroma_key = 7, > + .chroma_key_mask = 8, > + .general_config = 9, > + }, > + .clut_offset = 0xb00, > + }, > + { > + .name = "overlay2", > + .formats = &atmel_hlcdc_plane_rgb_formats, > + .regs_offset = 0x260, > + .id = 2, > + .type = ATMEL_HLCDC_OVERLAY_LAYER, > + .cfgs_offset = 0x1c, > + .layout = { > + .pos = 2, > + .size = 3, > + .xstride = { 4 }, > + .pstride = { 5 }, > + .default_color = 6, > + .chroma_key = 7, > + .chroma_key_mask = 8, > + .general_config = 9, > + }, > + .clut_offset = 0xf00, > + }, > + { > + .name = "high-end-overlay", > + .formats = &atmel_hlcdc_plane_rgb_and_yuv_formats, > + .regs_offset = 0x360, > + .id = 3, > + .type = ATMEL_HLCDC_OVERLAY_LAYER, > + .cfgs_offset = 0x30, > + .layout = { > + .pos = 2, > + .size = 3, > + .memsize = 4, > + .xstride = { 5, 7 }, > + .pstride = { 6, 8 }, > + .default_color = 9, > + .chroma_key = 10, > + .chroma_key_mask = 11, > + .general_config = 12, > + .csc = 16, > + .scaler_config = 23, > + }, > + .clut_offset = 0x1300, > + }, > +}; > + > +static const struct atmel_hlcdc_dc_desc atmel_xlcdc_dc_sam9x75 = { > + .min_width = 0, > + .min_height = 0, > + .max_width = 2048, > + .max_height = 2048, > + .max_spw = 0xff, > + .max_vpw = 0xff, > + .max_hpw = 0x3ff, > + .fixed_clksrc = true, > + .is_xlcdc = true, > + .nlayers = ARRAY_SIZE(atmel_xlcdc_sam9x75_layers), > + .layers = atmel_xlcdc_sam9x75_layers, > +}; > + > static const struct of_device_id atmel_hlcdc_of_match[] = { > { > .compatible = "atmel,at91sam9n12-hlcdc", > @@ -487,6 +580,10 @@ static const struct of_device_id atmel_hlcdc_of_match[] = { > .compatible = "microchip,sam9x60-hlcdc", > .data = &atmel_hlcdc_dc_sam9x60, > }, > + { > + .compatible = "microchip,sam9x75-xlcdc", > + .data = &atmel_xlcdc_dc_sam9x75, > + }, > { /* sentinel */ }, > }; > MODULE_DEVICE_TABLE(of, atmel_hlcdc_of_match);