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Message-ID: <2678d8a5-4101-4fc3-9f9d-cbe616eee131@linaro.org>
Date:   Mon, 25 Sep 2023 10:51:27 +0200
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Subject: Re: [PATCH 3/4] clk: qcom: camcc-sc8280xp: Add sc8280xp CAMCC
To:     Bryan O'Donoghue <bryan.odonoghue@linaro.org>,
        andersson@kernel.org, agross@kernel.org, mturquette@baylibre.com,
        sboyd@kernel.org, robh+dt@kernel.org,
        krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org,
        jonathan@marek.ca, quic_tdas@quicinc.com,
        vladimir.zapolskiy@linaro.org
Cc:     linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org,
        devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
References: <20230923150045.1068556-1-bryan.odonoghue@linaro.org>
 <20230923150045.1068556-4-bryan.odonoghue@linaro.org>
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From:   Konrad Dybcio <konrad.dybcio@linaro.org>
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In-Reply-To: <20230923150045.1068556-4-bryan.odonoghue@linaro.org>
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On 23.09.2023 17:00, Bryan O'Donoghue wrote:
> Add the sc8280xp CAMCC driver which follows the sdm845 CAMCC lineage
> with additional CCI and IFE blocks and more granular clock parentage.
> 
> Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
> ---
>  drivers/clk/qcom/Kconfig          |    9 +
>  drivers/clk/qcom/Makefile         |    1 +
>  drivers/clk/qcom/camcc-sc8280xp.c | 3051 +++++++++++++++++++++++++++++
>  3 files changed, 3061 insertions(+)
>  create mode 100644 drivers/clk/qcom/camcc-sc8280xp.c
> 
> diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
> index 4b72e98eaa70..5ce6d888aba0 100644
> --- a/drivers/clk/qcom/Kconfig
> +++ b/drivers/clk/qcom/Kconfig
> @@ -426,6 +426,15 @@ config SC_CAMCC_7280
>  	  Say Y if you want to support camera devices and functionality such as
>  	  capturing pictures.
>  
> +config SC_CAMCC_8280XP
> +	tristate "SC8280XP Camera Clock Controller"
> +	select SC_GCC_8280XP
> +	help
> +	  Support for the camera clock controller on Qualcomm Technologies, Inc
> +	  SC8280XP devices.
> +	  Say Y if you want to support camera devices and functionality such as
> +	  capturing pictures.
> +
>  config SC_DISPCC_7180
>  	tristate "SC7180 Display Clock Controller"
>  	depends on ARM64 || COMPILE_TEST
> diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
> index a301b08dba05..8f66cefa9e57 100644
> --- a/drivers/clk/qcom/Makefile
> +++ b/drivers/clk/qcom/Makefile
> @@ -68,6 +68,7 @@ obj-$(CONFIG_QCS_TURING_404) += turingcc-qcs404.o
>  obj-$(CONFIG_QDU_GCC_1000) += gcc-qdu1000.o
>  obj-$(CONFIG_SC_CAMCC_7180) += camcc-sc7180.o
>  obj-$(CONFIG_SC_CAMCC_7280) += camcc-sc7280.o
> +obj-$(CONFIG_SC_CAMCC_8280XP) += camcc-sc8280xp.o
>  obj-$(CONFIG_SC_DISPCC_7180) += dispcc-sc7180.o
>  obj-$(CONFIG_SC_DISPCC_7280) += dispcc-sc7280.o
>  obj-$(CONFIG_SC_DISPCC_8280XP) += dispcc-sc8280xp.o
> diff --git a/drivers/clk/qcom/camcc-sc8280xp.c b/drivers/clk/qcom/camcc-sc8280xp.c
> new file mode 100644
> index 000000000000..fbb3fa39862c
> --- /dev/null
> +++ b/drivers/clk/qcom/camcc-sc8280xp.c
> @@ -0,0 +1,3051 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2021, The Linux Foundation. All rights reserved.
> + * Copyright (c) 2023, Linaro Ltd.
> + */
> +
> +#include <linux/clk-provider.h>
> +#include <linux/err.h>
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/of_device.h>
> +#include <linux/of.h>
> +#include <linux/pm_clock.h>
> +#include <linux/pm_runtime.h>
> +#include <linux/regmap.h>
> +#include <linux/pm_runtime.h>
> +
> +#include <dt-bindings/clock/qcom,camcc-sc8280xp.h>
> +
> +#include "clk-alpha-pll.h"
> +#include "clk-branch.h"
> +#include "clk-rcg.h"
> +#include "clk-regmap.h"
> +#include "common.h"
> +#include "gdsc.h"
> +#include "reset.h"
> +
> +enum {
> +	DT_BI_TCXO,
> +	DT_BI_TCXO_AO,
> +	DT_SLEEP_CLK,
> +};
This enum here is so that

[...]

> +static struct clk_alpha_pll cam_cc_pll0 = {
> +	.offset = 0x0,
> +	.vco_table = lucid_vco,
> +	.num_vco = ARRAY_SIZE(lucid_vco),
> +	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
> +	.clkr = {
> +		.hw.init = &(struct clk_init_data){
> +			.name = "cam_cc_pll0",
> +			.parent_data = &(const struct clk_parent_data){
> +				.fw_name = "bi_tcxo", .name = "bi_tcxo",
you can use .index = <some enum member> here


[...]

> +
> +static const struct clk_parent_data cam_cc_parent_data_0[] = {
> +	{ .fw_name = "bi_tcxo", .name = "bi_tcxo" },
also in these arrays

[...]

> +static struct gdsc bps_gdsc = {
> +	.gdscr = 0x7004,
> +	.pd = {
> +		.name = "bps_gdsc",
> +	},
> +	.flags = HW_CTRL | RETAIN_FF_ENABLE,
HW_CTRL means "hardware controlled mode is always on", not
"hardware controlled mode is available". Is that what you want?

Also, does this clock controller not take GCC_CAMERA_AHB_CLK as
input?

Konrad