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In-Reply-To: <64e91f8d-a94e-c835-75ef-ce9ab557dc54@tuxon.dev>
From:   Geert Uytterhoeven <geert@linux-m68k.org>
Date:   Tue, 26 Sep 2023 16:29:05 +0200
Message-ID: <CAMuHMdV_xdNtM3Qv+9iqiyHCALMPx4DzC4-DWbXLCtum-LS_Hw@mail.gmail.com>
Subject: Re: [PATCH 30/37] pinctrl: renesas: rzg2l: add support for RZ/G3S SoC
To:     claudiu beznea <claudiu.beznea@tuxon.dev>
Cc:     mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org,
        krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org,
        ulf.hansson@linaro.org, linus.walleij@linaro.org,
        gregkh@linuxfoundation.org, jirislaby@kernel.org,
        magnus.damm@gmail.com, catalin.marinas@arm.com, will@kernel.org,
        prabhakar.mahadev-lad.rj@bp.renesas.com,
        biju.das.jz@bp.renesas.com, quic_bjorande@quicinc.com,
        arnd@arndb.de, konrad.dybcio@linaro.org, neil.armstrong@linaro.org,
        nfraprado@collabora.com, rafal@milecki.pl,
        wsa+renesas@sang-engineering.com,
        linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org,
        devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
        linux-mmc@vger.kernel.org, linux-gpio@vger.kernel.org,
        linux-serial@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
        Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
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Hi Claudiu,

On Tue, Sep 26, 2023 at 12:58 PM claudiu beznea
<claudiu.beznea@tuxon.dev> wrote:
> On 21.09.2023 17:58, Geert Uytterhoeven wrote:
> > On Tue, Sep 12, 2023 at 6:53 AM Claudiu <claudiu.beznea@tuxon.dev> wrote:
> >> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> >>
> >> Add basic support for RZ/G3S to be able to boot from SD card, have a
> >> running console port and use GPIOs. RZ/G3S has 82 general-purpose IO
> >> ports. Support for the remaining pin functions (e.g. Ethernet, XSPI)
> >> will be added along with controller specific support.
> >>
> >> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> >
> > Thanks for your patch!
> >
> >> --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> >> +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> >> @@ -1330,6 +1336,36 @@ static const u32 r9a07g043_gpio_configs[] = {
> >>         RZG2L_GPIO_PORT_PACK(6, 0x22, RZG2L_MPXED_PIN_FUNCS),
> >>  };
> >>
> >> +static const u32 r9a08g045_gpio_configs[] = {
> >> +       RZG2L_GPIO_PORT_PACK(4, 0x20, RZG3S_MPXED_PIN_FUNCS(A)),                        /* P0  */
> >> +       RZG2L_GPIO_PORT_PACK(5, 0x30, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C |
> >> +                                                               PIN_CFG_IO_VMC_ETH0)),  /* P1 */
> >
> > P1_0 and P7_0 have IEN functionality.
> > I don't know how to represent that...
>
> I think Prabhakar's series at [1] may help (or make a step forward) in
> supporting this. I have in mind to wait for it and adapt RZ/G3S afterwards.

OK.

> [1]
> https://lore.kernel.org/all/20230630120433.49529-2-prabhakar.mahadev-lad.rj@bp.renesas.com/

> > Is there any specific reason you left out the XSPI, Audio clock, and I3C pins?
>
> I kept only the necessary support for booting and having SDs, GPIO
> functional as a way of proving that all that has been added has been tested
> (similar to clock support). Thus, with e.g. XSPI support I will add at the
> same time clocks and pinctrl.

IC.  I all fairness, you did write in your patch description that support
for e.g. XSPI will be added later, so I'm to blame here.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds