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From:   <Shravan.Chippa@microchip.com>
To:     <conor@kernel.org>
CC:     <green.wan@sifive.com>, <vkoul@kernel.org>, <robh+dt@kernel.org>,
        <krzysztof.kozlowski+dt@linaro.org>, <palmer@dabbelt.com>,
        <paul.walmsley@sifive.com>, <conor+dt@kernel.org>,
        <palmer@sifive.com>, <dmaengine@vger.kernel.org>,
        <devicetree@vger.kernel.org>, <linux-riscv@lists.infradead.org>,
        <linux-kernel@vger.kernel.org>, <Nagasuresh.Relli@microchip.com>,
        <Praveen.Kumar@microchip.com>, <Conor.Dooley@microchip.com>
Subject: RE: [PATCH v1 3/3] dmaengine: sf-pdma: add mpfs-pdma compatible name
Thread-Topic: [PATCH v1 3/3] dmaengine: sf-pdma: add mpfs-pdma compatible name
Thread-Index: AQHZ7TpYtoHe5V6jCkaV0cVSgcPUurAmncAAgAYXIuA=
Date:   Tue, 26 Sep 2023 07:04:22 +0000
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References: <20230922095039.74878-1-shravan.chippa@microchip.com>
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Hi,

> -----Original Message-----
> From: Conor Dooley <conor@kernel.org>
> Sent: Friday, September 22, 2023 3:34 PM
> To: shravan Chippa - I35088 <Shravan.Chippa@microchip.com>
> Cc: green.wan@sifive.com; vkoul@kernel.org; robh+dt@kernel.org;
> krzysztof.kozlowski+dt@linaro.org; palmer@dabbelt.com;
> paul.walmsley@sifive.com; conor+dt@kernel.org; palmer@sifive.com;
> dmaengine@vger.kernel.org; devicetree@vger.kernel.org; linux-
> riscv@lists.infradead.org; linux-kernel@vger.kernel.org; Nagasuresh Relli=
 -
> I67208 <Nagasuresh.Relli@microchip.com>; Praveen Kumar - I30718
> <Praveen.Kumar@microchip.com>; Conor Dooley - M52691
> <Conor.Dooley@microchip.com>
> Subject: Re: [PATCH v1 3/3] dmaengine: sf-pdma: add mpfs-pdma compatible
> name
>=20
> Hey Shravan,
>=20
> On Fri, Sep 22, 2023 at 03:20:39PM +0530, shravan chippa wrote:
> > From: Shravan Chippa <shravan.chippa@microchip.com>
> >
> > Sifive platform dma does not allow out-of-order transfers,
>=20
> Can you remind me why we determined that this was the case?
> IOW, why could we not enable the out-of-order transfers and get a
> performance benefit for everyone? It's been a year or so (I think) and I =
have
> forgotten.

sf-dma is used for all Sifive RISC-V chipsets, but we will not be able to t=
est on all of them
in the microchip polar-fire FPGA SOC (RISC-V) platform we got good throughp=
ut with out-off-order transfers.
so we thought of having a separate compatible name for sf-dma driver to use=
 out-of-order transfers.=20

Thanks,
Shravan

>=20
> Cheers,
> Conor.
>=20
> > buf out-of-order dma has a significant performance advantage.
> > Add a PolarFire SoC specific compatible and code to support for
> > out-of-order dma transfers
> >
> > Signed-off-by: Shravan Chippa <shravan.chippa@microchip.com>
> > Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
> > Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> > ---
> >  drivers/dma/sf-pdma/sf-pdma.c | 27 ++++++++++++++++++++++++---
> > drivers/dma/sf-pdma/sf-pdma.h |  6 ++++++
> >  2 files changed, 30 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/dma/sf-pdma/sf-pdma.c
> > b/drivers/dma/sf-pdma/sf-pdma.c index c7558c9f9ac3..992a804166d5
> > 100644
> > --- a/drivers/dma/sf-pdma/sf-pdma.c
> > +++ b/drivers/dma/sf-pdma/sf-pdma.c
> > @@ -21,6 +21,7 @@
> >  #include <linux/dma-mapping.h>
> >  #include <linux/of.h>
> >  #include <linux/of_dma.h>
> > +#include <linux/of_device.h>
> >  #include <linux/slab.h>
> >
> >  #include "sf-pdma.h"
> > @@ -66,7 +67,7 @@ static struct sf_pdma_desc
> > *sf_pdma_alloc_desc(struct sf_pdma_chan *chan)  static void
> sf_pdma_fill_desc(struct sf_pdma_desc *desc,
> >  			      u64 dst, u64 src, u64 size)
> >  {
> > -	desc->xfer_type =3D PDMA_FULL_SPEED;
> > +	desc->xfer_type =3D  desc->chan->pdma->transfer_type;
> >  	desc->xfer_size =3D size;
> >  	desc->dst_addr =3D dst;
> >  	desc->src_addr =3D src;
> > @@ -520,6 +521,7 @@ static struct dma_chan *sf_pdma_of_xlate(struct
> > of_phandle_args *dma_spec,
> >
> >  static int sf_pdma_probe(struct platform_device *pdev)  {
> > +	const struct sf_pdma_driver_platdata *ddata;
> >  	struct sf_pdma *pdma;
> >  	int ret, n_chans;
> >  	const enum dma_slave_buswidth widths =3D @@ -545,6 +547,14 @@
> static
> > int sf_pdma_probe(struct platform_device *pdev)
> >
> >  	pdma->n_chans =3D n_chans;
> >
> > +	pdma->transfer_type =3D PDMA_FULL_SPEED;
> > +
> > +	ddata  =3D of_device_get_match_data(&pdev->dev);
> > +	if (ddata) {
> > +		if (ddata->quirks & NO_STRICT_ORDERING)
> > +			pdma->transfer_type &=3D ~(NO_STRICT_ORDERING);
> > +	}
> > +
> >  	pdma->membase =3D devm_platform_ioremap_resource(pdev, 0);
> >  	if (IS_ERR(pdma->membase))
> >  		return PTR_ERR(pdma->membase);
> > @@ -629,11 +639,22 @@ static int sf_pdma_remove(struct
> platform_device *pdev)
> >  	return 0;
> >  }
> >
> > +static const struct sf_pdma_driver_platdata mpfs_pdma =3D {
> > +	.quirks =3D NO_STRICT_ORDERING,
> > +};
> > +
> >  static const struct of_device_id sf_pdma_dt_ids[] =3D {
> > -	{ .compatible =3D "sifive,fu540-c000-pdma" },
> > -	{ .compatible =3D "sifive,pdma0" },
> > +	{
> > +		.compatible =3D "sifive,fu540-c000-pdma",
> > +	}, {
> > +		.compatible =3D "sifive,pdma0",
> > +	}, {
> > +		.compatible =3D "microchip,mpfs-pdma",
> > +		.data	    =3D &mpfs_pdma,
> > +	},
> >  	{},
> >  };
> > +
> >  MODULE_DEVICE_TABLE(of, sf_pdma_dt_ids);
> >
> >  static struct platform_driver sf_pdma_driver =3D { diff --git
> > a/drivers/dma/sf-pdma/sf-pdma.h b/drivers/dma/sf-pdma/sf-pdma.h
> index
> > 5c398a83b491..3b16db4daa0b 100644
> > --- a/drivers/dma/sf-pdma/sf-pdma.h
> > +++ b/drivers/dma/sf-pdma/sf-pdma.h
> > @@ -49,6 +49,7 @@
> >
> >  /* Transfer Type */
> >  #define PDMA_FULL_SPEED					0xFF000008
> > +#define NO_STRICT_ORDERING				BIT(3)
> >
> >  /* Error Recovery */
> >  #define MAX_RETRY					1
> > @@ -112,8 +113,13 @@ struct sf_pdma {
> >  	struct dma_device       dma_dev;
> >  	void __iomem            *membase;
> >  	void __iomem            *mappedbase;
> > +	u32			transfer_type;
> >  	u32			n_chans;
> >  	struct sf_pdma_chan	chans[];
> >  };
> >
> > +struct sf_pdma_driver_platdata {
> > +	u32 quirks;
> > +};
> > +
> >  #endif /* _SF_PDMA_H */
> > --
> > 2.34.1
> >