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Date:   Tue, 26 Sep 2023 19:11:43 +0300 (EEST)
From:   =?ISO-8859-15?Q?Ilpo_J=E4rvinen?= <ilpo.jarvinen@linux.intel.com>
To:     "David E. Box" <david.e.box@linux.intel.com>
cc:     linux-kernel@vger.kernel.org, platform-driver-x86@vger.kernel.org,
        ilpo.jarvinen@linux.intel.com, rajvi.jingar@linux.intel.com
Subject: Re: [PATCH 11/11] platform/x86/intel/pmc: Add debug attribute for
 Die C6 counter
In-Reply-To: <20230922213032.1770590-12-david.e.box@linux.intel.com>
Message-ID: <65178530-1635-61c7-f7e2-ff3fb4d584d@linux.intel.com>
References: <20230922213032.1770590-1-david.e.box@linux.intel.com> <20230922213032.1770590-12-david.e.box@linux.intel.com>
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On Fri, 22 Sep 2023, David E. Box wrote:

> Add a "die_c6_us_show" counter in debugs and add support for Meteor Lake.
> Reads the counter value using Intel Platform Monitoring Technology (PMT)
> driver API. This counter is useful for determining the idle residency of
> CPUs in the compute tile.
> 
> Signed-off-by: David E. Box <david.e.box@linux.intel.com>
> ---
>  drivers/platform/x86/intel/pmc/core.c | 55 +++++++++++++++++++++++++++
>  drivers/platform/x86/intel/pmc/core.h |  4 ++
>  drivers/platform/x86/intel/pmc/mtl.c  | 32 ++++++++++++++++
>  3 files changed, 91 insertions(+)
> 
> diff --git a/drivers/platform/x86/intel/pmc/core.c b/drivers/platform/x86/intel/pmc/core.c
> index df2bcead1723..790ed9481529 100644
> --- a/drivers/platform/x86/intel/pmc/core.c
> +++ b/drivers/platform/x86/intel/pmc/core.c
> @@ -27,6 +27,7 @@
>  #include <asm/tsc.h>
>  
>  #include "core.h"
> +#include "../pmt/telemetry.h"
>  
>  /* Maximum number of modes supported by platfoms that has low power mode capability */
>  const char *pmc_lpm_modes[] = {
> @@ -822,6 +823,48 @@ static int pmc_core_substate_req_regs_show(struct seq_file *s, void *unused)
>  }
>  DEFINE_SHOW_ATTRIBUTE(pmc_core_substate_req_regs);
>  
> +static unsigned int pmc_core_get_crystal_freq(void)
> +{
> +	unsigned int eax_denominator, ebx_numerator, ecx_hz, edx;
> +
> +	if (boot_cpu_data.cpuid_level < 0x15)
> +		return 0;
> +
> +	eax_denominator = ebx_numerator = ecx_hz = edx = 0;
> +
> +	/* CPUID 15H TSC/Crystal ratio, plus optionally Crystal Hz */
> +	cpuid(0x15, &eax_denominator, &ebx_numerator, &ecx_hz, &edx);
> +
> +	if (ebx_numerator == 0 || eax_denominator == 0)
> +		return 0;
> +
> +	return ecx_hz;
> +}
> +
> +static int pmc_core_die_c6_us_show(struct seq_file *s, void *unused)
> +{
> +	struct pmc_dev *pmcdev = s->private;
> +	u64 die_c6_res, count;
> +	int ret;
> +
> +	if (!pmcdev->crystal_freq) {
> +		dev_warn_once(&pmcdev->pdev->dev, "%s: Bad crystal frequency\n",
> +			      __func__);

Don't use __func__.

> +		return -EINVAL;
> +	}
> +
> +	ret = pmt_telem_read(pmcdev->punit_ep, pmcdev->die_c6_offset,
> +			     &count, 1);
> +	if (ret)
> +		return ret;
> +
> +	die_c6_res = div64_u64(count * 1000000ULL, pmcdev->crystal_freq);

HZ_PER_MHZ ?

> +	seq_printf(s, "%llu\n", die_c6_res);
> +
> +	return 0;
> +}
> +DEFINE_SHOW_ATTRIBUTE(pmc_core_die_c6_us);
> +
>  static int pmc_core_lpm_latch_mode_show(struct seq_file *s, void *unused)
>  {
>  	struct pmc_dev *pmcdev = s->private;
> @@ -1118,6 +1161,12 @@ static void pmc_core_dbgfs_register(struct pmc_dev *pmcdev)
>  				    pmcdev->dbgfs_dir, pmcdev,
>  				    &pmc_core_substate_req_regs_fops);
>  	}
> +
> +	if (pmcdev->has_die_c6) {
> +		debugfs_create_file("die_c6_us_show", 0444,
> +				    pmcdev->dbgfs_dir, pmcdev,
> +				    &pmc_core_die_c6_us_fops);
> +	}
>  }
>  
>  static const struct x86_cpu_id intel_pmc_core_ids[] = {
> @@ -1212,6 +1261,10 @@ static void pmc_core_clean_structure(struct platform_device *pdev)
>  		pci_dev_put(pmcdev->ssram_pcidev);
>  		pci_disable_device(pmcdev->ssram_pcidev);
>  	}
> +
> +	if (pmcdev->punit_ep)
> +		pmt_telem_unregister_endpoint(pmcdev->punit_ep);
> +
>  	platform_set_drvdata(pdev, NULL);
>  	mutex_destroy(&pmcdev->lock);
>  }
> @@ -1232,6 +1285,8 @@ static int pmc_core_probe(struct platform_device *pdev)
>  	if (!pmcdev)
>  		return -ENOMEM;
>  
> +	pmcdev->crystal_freq = pmc_core_get_crystal_freq();
> +
>  	platform_set_drvdata(pdev, pmcdev);
>  	pmcdev->pdev = pdev;
>  
> diff --git a/drivers/platform/x86/intel/pmc/core.h b/drivers/platform/x86/intel/pmc/core.h
> index 85b6f6ae4995..6d7673145f90 100644
> --- a/drivers/platform/x86/intel/pmc/core.h
> +++ b/drivers/platform/x86/intel/pmc/core.h
> @@ -16,6 +16,8 @@
>  #include <linux/bits.h>
>  #include <linux/platform_device.h>
>  
> +struct telem_endpoint;
> +
>  #define SLP_S0_RES_COUNTER_MASK			GENMASK(31, 0)
>  
>  #define PMC_BASE_ADDR_DEFAULT			0xFE000000
> @@ -357,6 +359,7 @@ struct pmc {
>   * @devs:		pointer to an array of pmc pointers
>   * @pdev:		pointer to platform_device struct
>   * @ssram_pcidev:	pointer to pci device struct for the PMC SSRAM
> + * @crystal_freq:	crystal frequency from cpuid
>   * @dbgfs_dir:		path to debugfs interface
>   * @pmc_xram_read_bit:	flag to indicate whether PMC XRAM shadow registers
>   *			used to read MPHY PG and PLL status are available
> @@ -374,6 +377,7 @@ struct pmc_dev {
>  	struct dentry *dbgfs_dir;
>  	struct platform_device *pdev;
>  	struct pci_dev *ssram_pcidev;
> +	unsigned int crystal_freq;
>  	int pmc_xram_read_bit;
>  	struct mutex lock; /* generic mutex lock for PMC Core */
>  
> diff --git a/drivers/platform/x86/intel/pmc/mtl.c b/drivers/platform/x86/intel/pmc/mtl.c
> index c2ac50cfdd51..d791d4894c9d 100644
> --- a/drivers/platform/x86/intel/pmc/mtl.c
> +++ b/drivers/platform/x86/intel/pmc/mtl.c
> @@ -10,12 +10,17 @@
>  
>  #include <linux/pci.h>
>  #include "core.h"
> +#include "../pmt/telemetry.h"
>  
>  /* PMC SSRAM PMT Telemetry GUIDS */
>  #define SOCP_LPM_REQ_GUID	0x2625030
>  #define IOEM_LPM_REQ_GUID	0x4357464
>  #define IOEP_LPM_REQ_GUID	0x5077612
>  
> +/* Die C6 from PUNIT telemetry */
> +#define MTL_PMT_DMU_DIE_C6_OFFSET	15
> +#define MTL_PMT_DMU_GUID		0x1A067102
> +
>  static const u8 MTL_LPM_REG_INDEX[] = {0, 4, 5, 6, 8, 9, 10, 11, 12, 13, 14, 15, 16, 20};
>  
>  /*
> @@ -968,6 +973,32 @@ static struct pmc_info mtl_pmc_info_list[] = {
>  	{}
>  };
>  
> +static void mtl_punit_pmt_init(struct pmc_dev *pmcdev)
> +{
> +	struct telem_endpoint *ep;
> +	struct pci_dev *pcidev;
> +
> +	pcidev = pci_get_domain_bus_and_slot(0, 0, PCI_DEVFN(10, 0));
> +	if (!pcidev) {
> +		dev_err(&pmcdev->pdev->dev, "PUNIT PMT device not found.");
> +		return;
> +	}
> +
> +	ep = pmt_telem_find_and_register_endpoint(pcidev, MTL_PMT_DMU_GUID, 0);
> +	if (IS_ERR(ep)) {
> +		dev_err(&pmcdev->pdev->dev,
> +			"pmc_core: couldn't get DMU telem endpoint %ld",

Missing \n from this and the previous dev_err().

> +			PTR_ERR(ep));
> +		return;
> +	}
> +
> +	pci_dev_put(pcidev);
> +	pmcdev->punit_ep = ep;
> +
> +	pmcdev->has_die_c6 = true;
> +	pmcdev->die_c6_offset = MTL_PMT_DMU_DIE_C6_OFFSET;
> +}
> +
>  #define MTL_GNA_PCI_DEV	0x7e4c
>  #define MTL_IPU_PCI_DEV	0x7d19
>  #define MTL_VPU_PCI_DEV	0x7d1d
> @@ -1030,6 +1061,7 @@ int mtl_core_init(struct pmc_dev *pmcdev)
>  	}
>  
>  	pmc_core_get_low_power_modes(pmcdev);
> +	mtl_punit_pmt_init(pmcdev);
>  
>  	/* Due to a hardware limitation, the GBE LTR blocks PC10
>  	 * when a cable is attached. Tell the PMC to ignore it.
> 

-- 
 i.