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[209.85.128.177]) by smtp.gmail.com with ESMTPSA id y4-20020a5b0f44000000b00d7e3e42d0c4sm259519ybr.53.2023.09.27.02.44.30 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 27 Sep 2023 02:44:30 -0700 (PDT) Received: by mail-yw1-f177.google.com with SMTP id 00721157ae682-59f6041395dso93370477b3.1; Wed, 27 Sep 2023 02:44:30 -0700 (PDT) X-Received: by 2002:a81:80c1:0:b0:59f:4bc3:3e9 with SMTP id q184-20020a8180c1000000b0059f4bc303e9mr1707738ywf.46.1695807870658; Wed, 27 Sep 2023 02:44:30 -0700 (PDT) MIME-Version: 1.0 References: <20230926210818.197356-1-fabrizio.castro.jz@renesas.com> <20230926210818.197356-2-fabrizio.castro.jz@renesas.com> In-Reply-To: From: Geert Uytterhoeven Date: Wed, 27 Sep 2023 11:44:17 +0200 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH 1/2] spi: renesas,rzv2m-csi: Add SPI Slave related properties To: Mark Brown Cc: Fabrizio Castro , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Magnus Damm , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Chris Paterson , Biju Das , Lad Prabhakar Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8BIT X-Spam-Status: No, score=-0.8 required=5.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lipwig.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (lipwig.vger.email [0.0.0.0]); Wed, 27 Sep 2023 02:44:47 -0700 (PDT) Hi Mark, On Wed, Sep 27, 2023 at 11:21 AM Mark Brown wrote: > On Wed, Sep 27, 2023 at 11:10:58AM +0200, Geert Uytterhoeven wrote: > > On Wed, Sep 27, 2023 at 11:00 AM Mark Brown wrote: > > > > The description is clearly saying there is a chip select, _NO_CS seems > > > entirely inappropriate. It's not specified in the device tree because > > > when there's no chip select for a device it's a fundamental property of > > > how the device is controlled and we don't need any information beyond > > > the compatible. > > > In host mode, it indeed doesn't matter, as you can have only a single > > device connected with SPI_NO_CS. > > In device mode, the device needs to know if it must monitor the chip > > select line or not. > > > In hindsight, I should have kept the question I had written initially, > > but deleted after having read the documentation for the corresponding > > RZ/V2M register bits: > > > What does it mean if this is false? That there is no chip select? > > > So "spi-no-cs" would be the inverse of "renesas,csi-ss". > > I see. Is there any control over what the chip select is when there is > one, in which case we could just look to see if there's one specified? On RZ/V2M there isn't, as there is only a single hardware chip select. On MSIOF, there are 3 hardware chip selects, but apparently only the primary one can be used in target mode. I have to admit I never thought about this before (commit cf9e4784f3bde3e4 ("spi: sh-msiof: Add slave mode support") also predates commit 9cce882bedd2768d ("spi: sh-msiof: Extend support to 3 native chip selects")). Hence the SPI target DT bindings use a single "slave" subnode, without a unit address, thus assuming no explicit (or a default) chip select configuration. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds