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Date:   Wed, 27 Sep 2023 16:33:44 +0800
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Subject: Re: [PATCH v3 01/11] riscv: Add SOPHGO SOC family Kconfig support
To:     Chen Wang <unicornxw@gmail.com>, aou@eecs.berkeley.edu,
        chao.wei@sophgo.com, conor@kernel.org, devicetree@vger.kernel.org,
        guoren@kernel.org, jszhang@kernel.org,
        krzysztof.kozlowski+dt@linaro.org, linux-kernel@vger.kernel.org,
        linux-riscv@lists.infradead.org, palmer@dabbelt.com,
        paul.walmsley@sifive.com, robh+dt@kernel.org,
        xiaoguang.xing@sophgo.com, apatel@ventanamicro.com
Cc:     Conor Dooley <conor.dooley@microchip.com>,
        Chen Wang <wangchen20@iscas.ac.cn>
References: <cover.1695800389.git.unicornxw@gmail.com>
 <bfa07dce9eb268b312bd64059773acf055727f17.1695800389.git.unicornxw@gmail.com>
From:   Chen Wang <unicorn_wang@outlook.com>
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Sorry, please ignore this email, the subject of this email is wrong, I 
will re-send another one.

在 2023/9/27 16:28, Chen Wang 写道:
> The first SoC in the SOPHGO series is SG2042, which contains 64 RISC-V
> cores.
>
> Reviewed-by: Guo Ren <guoren@kernel.org>
> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
> Acked-by: Chao Wei <chao.wei@sophgo.com>
> Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
> Signed-off-by: Chen Wang <unicornxw@gmail.com>
> ---
>   arch/riscv/Kconfig.socs | 5 +++++
>   1 file changed, 5 insertions(+)
>
> diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
> index 6833d01e2e70..d4df7b5d0f16 100644
> --- a/arch/riscv/Kconfig.socs
> +++ b/arch/riscv/Kconfig.socs
> @@ -22,6 +22,11 @@ config SOC_SIFIVE
>   	help
>   	  This enables support for SiFive SoC platform hardware.
>   
> +config ARCH_SOPHGO
> +	bool "Sophgo SoCs"
> +	help
> +	  This enables support for Sophgo SoC platform hardware.
> +
>   config ARCH_STARFIVE
>   	def_bool SOC_STARFIVE
>