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Wed, 27 Sep 2023 05:39:37 -0700 (PDT) Date: Wed, 27 Sep 2023 14:39:34 +0200 From: Manivannan Sadhasivam To: Viresh Kumar Cc: Dmitry Baryshkov , vireshk@kernel.org, nm@ti.com, sboyd@kernel.org, myungjoo.ham@samsung.com, kyungmin.park@samsung.com, cw00.choi@samsung.com, andersson@kernel.org, konrad.dybcio@linaro.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, jejb@linux.ibm.com, martin.petersen@oracle.com, alim.akhtar@samsung.com, avri.altman@wdc.com, bvanassche@acm.org, linux-scsi@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, quic_asutoshd@quicinc.com, quic_cang@quicinc.com, quic_nitirawa@quicinc.com, quic_narepall@quicinc.com, quic_bhaskarv@quicinc.com, quic_richardp@quicinc.com, quic_nguyenb@quicinc.com, quic_ziqichen@quicinc.com, bmasney@redhat.com, krzysztof.kozlowski@linaro.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v3 5/6] arm64: dts: qcom: sdm845: Add OPP table support to UFSHC Message-ID: <20230927123934.GA18050@thinkpad> References: <20230731163357.49045-1-manivannan.sadhasivam@linaro.org> <20230731163357.49045-6-manivannan.sadhasivam@linaro.org> <04eb9f71-78f0-41f2-96a6-fc759ba296fa@linaro.org> <20230912065918.GB6404@thinkpad> <20230927111546.uyaod34zcjr7npgf@vireshk-i7> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20230927111546.uyaod34zcjr7npgf@vireshk-i7> X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on pete.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (pete.vger.email [0.0.0.0]); Wed, 27 Sep 2023 05:39:51 -0700 (PDT) On Wed, Sep 27, 2023 at 04:45:46PM +0530, Viresh Kumar wrote: > On 12-09-23, 12:29, Manivannan Sadhasivam wrote: > > On Mon, Sep 11, 2023 at 04:15:10PM +0300, Dmitry Baryshkov wrote: > > > I'd say, I'm still slightly unhappy about the 0 clock rates here. > > > > Neither do I. But it is the only viable option I could found. > > > > > We need only three clocks here: core, core_clk_unipro and optional > > > ice_core_clk. Can we modify ufshcd_parse_operating_points() to pass only > > > these two or three clock names to devm_pm_opp_set_config() ? The OPP core > > > doesn't need to know about all the rest of the clocks. > > > > > > > We need to enable/disable all of the clocks, but only need to control the rate > > for these 3 clocks. So we cannot just use 3 clocks. > > > > If the OPP table has only 3 entries (omitting the gate-only clocks), then we > > need some hack in the driver to match the rates against the clock entries. Doing > > so will result in hardcoding the clock info in the driver which I do not want to > > do. > > > > If we have something like "opp-hz-names" to relate the rates to clock-names, it > > might do the job. But it needs some input from Viresh. > > I have already given an option earlier about this [1]. You can change the order > of clks in the "clock-names" field, so that the first three are the one with > valid frequencies. You shouldn't need much of the hacks after that I guess. > I do not remember all the details on the top of my head, but I did investigate on that and concluded that it won't fit. - Mani > Or maybe I missed something else now, talked about this a long time ago :) > > -- > viresh > [1] https://lore.kernel.org/all/20230713040918.jnf5oqiwymrdnrmq@vireshk-i7/ -- மணிவண்ணன் சதாசிவம்