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Subject: RE: [PATCH v5 07/11] iommufd: Add data structure for Intel VT-d
 stage-1 cache invalidation
Thread-Topic: [PATCH v5 07/11] iommufd: Add data structure for Intel VT-d
 stage-1 cache invalidation
Thread-Index: AQHZ7GDu37ctDRm8jEeyC19NQT1n7bAuQvxg
Date:   Wed, 27 Sep 2023 06:46:23 +0000
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> From: Liu, Yi L <yi.l.liu@intel.com>
> Sent: Thursday, September 21, 2023 3:54 PM
>=20
> +/**
> + * enum iommu_hwpt_vtd_s1_invalidate_flags - Flags for Intel VT-d
> + *                                           stage-1 cache invalidation
> + * @IOMMU_VTD_QI_FLAGS_LEAF: The LEAF flag indicates whether only the
> + *                           leaf PTE caching needs to be invalidated
> + *                           and other paging structure caches can be
> + *                           preserved.
> + */
> +enum iommu_hwpt_vtd_s1_invalidate_flags {
> +	IOMMU_VTD_QI_FLAGS_LEAF =3D 1 << 0,
> +};

QI is iommu driver internal term.

let's use IOMMU_VTD_INV_FLAGS_LEAF here.

> +
> +/**
> + * struct iommu_hwpt_vtd_s1_invalidate - Intel VT-d cache invalidation
> + *                                       (IOMMU_HWPT_TYPE_VTD_S1)
> + * @addr: The start address of the addresses to be invalidated.
> + * @npages: Number of contiguous 4K pages to be invalidated.
> + * @flags: Combination of enum iommu_hwpt_vtd_s1_invalidate_flags
> + * @__reserved: Must be 0
> + *
> + * The Intel VT-d specific invalidation data for user-managed stage-1 ca=
che
> + * invalidation under nested translation. Userspace uses this structure =
to

s/under/in/

> + * tell host about the impacted caches after modifying the stage-1 page
> table.

"to tell the impacted cache scope..."

> + *
> + * Invalidating all the caches related to the page table by setting @add=
r
> + * to be 0 and @npages to be __aligned_u64(-1).

This should also call out that device TLB is also invalidated by this reque=
st
if ATS is enabled on the device.