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Message-ID: <7f4f3e06-af20-4276-bcb9-6ad7acbf9c35@linaro.org>
Date:   Wed, 27 Sep 2023 11:59:47 +0100
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Subject: Re: [PATCH 1/4] arm64: dts: qcom: sm6375: Add UART1
Content-Language: en-US
To:     Konrad Dybcio <konrad.dybcio@linaro.org>,
        Andy Gross <agross@kernel.org>,
        Bjorn Andersson <andersson@kernel.org>,
        Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Conor Dooley <conor+dt@kernel.org>
Cc:     Marijn Suijten <marijn.suijten@somainline.org>,
        linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
        linux-kernel@vger.kernel.org
References: <20230927-topic-6375_stuff-v1-0-12243e36b45c@linaro.org>
 <20230927-topic-6375_stuff-v1-1-12243e36b45c@linaro.org>
From:   Bryan O'Donoghue <bryan.odonoghue@linaro.org>
In-Reply-To: <20230927-topic-6375_stuff-v1-1-12243e36b45c@linaro.org>
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Precedence: bulk

On 27/09/2023 10:21, Konrad Dybcio wrote:
> Add UART1 node, generally used for the Bluetooth module.
> 
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> ---
>   arch/arm64/boot/dts/qcom/sm6375.dtsi | 43 ++++++++++++++++++++++++++++++++++++
>   1 file changed, 43 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sm6375.dtsi b/arch/arm64/boot/dts/qcom/sm6375.dtsi
> index e7ff55443da7..2fba0e7ea4e6 100644
> --- a/arch/arm64/boot/dts/qcom/sm6375.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm6375.dtsi
> @@ -896,6 +896,36 @@ qup_spi0_default: qup-spi0-default-state {
>   				drive-strength = <6>;
>   				bias-disable;
>   			};
> +
> +			qup_uart1_default: qup-uart1-default-state {
> +				cts-pins {
> +					pins = "gpio61";
> +					function = "qup01";
> +					drive-strength = <2>;
> +					bias-pull-down;
> +				};

Any particular reason you are doing bias-pull-down here instead of

bias-disable ?

> +
> +				rts-pins {
> +					pins = "gpio62";
> +					function = "qup01";
> +					drive-strength = <2>;
> +					bias-disable;
> +				};
> +
> +				tx-pins {
> +					pins = "gpio63";
> +					function = "qup01";
> +					drive-strength = <2>;
> +					bias-disable;
> +				};
> +
> +				rx-pins {
> +					pins = "gpio64";
> +					function = "qup01";
> +					drive-strength = <2>;
> +					bias-pull-up;
> +				};
> +			};
>   		};
>   
>   		gcc: clock-controller@1400000 {
> @@ -1111,6 +1141,19 @@ spi1: spi@4a84000 {
>   				status = "disabled";
>   			};
>   
> +			uart1: serial@4a84000 {
> +				compatible = "qcom,geni-uart";
> +				reg = <0x0 0x04a84000 0x0 0x4000>;
> +				interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
> +				clock-names = "se";
> +				power-domains = <&rpmpd SM6375_VDDCX>;
> +				operating-points-v2 = <&qup_opp_table>;
> +				pinctrl-0 = <&qup_uart1_default>;
> +				pinctrl-names = "default";
> +				status = "disabled";
> +			};
> +
>   			i2c2: i2c@4a88000 {
>   				compatible = "qcom,geni-i2c";
>   				reg = <0x0 0x04a88000 0x0 0x4000>;
> 

Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>