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Date:   Wed, 27 Sep 2023 07:25:03 -0500
From:   Nishanth Menon <nm@ti.com>
To:     Jayesh Choudhary <j-choudhary@ti.com>
CC:     <vigneshr@ti.com>, <a-bhatia1@ti.com>, <afd@ti.com>,
        <rogerq@kernel.org>, <s-vadapalli@ti.com>, <conor+dt@kernel.org>,
        <r-ravikumar@ti.com>, <sabiya.d@ti.com>, <kristo@kernel.org>,
        <robh+dt@kernel.org>, <krzysztof.kozlowski+dt@linaro.org>,
        <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
        <linux-arm-kernel@lists.infradead.org>
Subject: Re: [PATCH v10 2/5] arm64: dts: ti: k3-j784s4-main: Add WIZ and
 SERDES PHY nodes
Message-ID: <20230927122503.cskdfnair5jtprdl@pennant>
References: <20230927121157.278592-1-j-choudhary@ti.com>
 <20230927121157.278592-3-j-choudhary@ti.com>
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On 17:41-20230927, Jayesh Choudhary wrote:
> From: Siddharth Vadapalli <s-vadapalli@ti.com>
> 
> J784S4 SoC has 4 Serdes instances along with their respective WIZ
> instances. Add device-tree nodes for them and disable them by default.
> 
> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
> [j-choudhary@ti.com: fix serdes_wiz clock order & disable serdes refclk]
> Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
> ---
>  arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 164 +++++++++++++++++++++
>  1 file changed, 164 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
> index 6d9a5a91fa75..a0e4d8808693 100644
> --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
> @@ -6,9 +6,19 @@
>   */
>  
>  #include <dt-bindings/mux/mux.h>
> +#include <dt-bindings/phy/phy.h>
> +#include <dt-bindings/phy/phy-ti.h>
>  
>  #include "k3-serdes.h"
>  
> +/ {
> +	serdes_refclk: clock-serdes {
> +		#clock-cells = <0>;
> +		compatible = "fixed-clock";
> +		status = "disabled";

Document why disabled. - same for rest of default disabled nodes.

> +	};
> +};
> +
>  &cbass_main {
>  	msmc_ram: sram@70000000 {
>  		compatible = "mmio-sram";
> @@ -709,6 +719,160 @@ main_sdhci1: mmc@4fb0000 {
>  		status = "disabled";
>  	};
>  
> +	serdes_wiz0: wiz@5060000 {
> +		compatible = "ti,j784s4-wiz-10g";
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		power-domains = <&k3_pds 404 TI_SCI_PD_EXCLUSIVE>;
> +		clocks = <&k3_clks 404 2>, <&k3_clks 404 6>, <&serdes_refclk>, <&k3_clks 404 5>;
> +		clock-names = "fck", "core_ref_clk", "ext_ref_clk", "core_ref1_clk";
> +		assigned-clocks = <&k3_clks 404 6>;
> +		assigned-clock-parents = <&k3_clks 404 10>;
> +		num-lanes = <4>;
> +		#reset-cells = <1>;
> +		#clock-cells = <1>;
> +		ranges = <0x5060000 0x00 0x5060000 0x10000>;
> +		status = "disabled";
> +
> +		serdes0: serdes@5060000 {
> +			compatible = "ti,j721e-serdes-10g";
> +			reg = <0x05060000 0x010000>;
> +			reg-names = "torrent_phy";
> +			resets = <&serdes_wiz0 0>;
> +			reset-names = "torrent_reset";
> +			clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
> +				 <&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>;
> +			clock-names = "refclk", "phy_en_refclk";
> +			assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
> +					  <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>,
> +					  <&serdes_wiz0 TI_WIZ_REFCLK_DIG>;
> +			assigned-clock-parents = <&k3_clks 404 6>,
> +						 <&k3_clks 404 6>,
> +						 <&k3_clks 404 6>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			#clock-cells = <1>;
> +			status = "disabled";
> +		};
> +	};
> +
> +	serdes_wiz1: wiz@5070000 {
> +		compatible = "ti,j784s4-wiz-10g";
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		power-domains = <&k3_pds 405 TI_SCI_PD_EXCLUSIVE>;
> +		clocks = <&k3_clks 405 2>, <&k3_clks 405 6>, <&serdes_refclk>, <&k3_clks 405 5>;
> +		clock-names = "fck", "core_ref_clk", "ext_ref_clk", "core_ref1_clk";
> +		assigned-clocks = <&k3_clks 405 6>;
> +		assigned-clock-parents = <&k3_clks 405 10>;
> +		num-lanes = <4>;
> +		#reset-cells = <1>;
> +		#clock-cells = <1>;
> +		ranges = <0x05070000 0x00 0x05070000 0x10000>;
> +		status = "disabled";
> +
> +		serdes1: serdes@5070000 {
> +			compatible = "ti,j721e-serdes-10g";
> +			reg = <0x05070000 0x010000>;
> +			reg-names = "torrent_phy";
> +			resets = <&serdes_wiz1 0>;
> +			reset-names = "torrent_reset";
> +			clocks = <&serdes_wiz1 TI_WIZ_PLL0_REFCLK>,
> +				 <&serdes_wiz1 TI_WIZ_PHY_EN_REFCLK>;
> +			clock-names = "refclk", "phy_en_refclk";
> +			assigned-clocks = <&serdes_wiz1 TI_WIZ_PLL0_REFCLK>,
> +					  <&serdes_wiz1 TI_WIZ_PLL1_REFCLK>,
> +					  <&serdes_wiz1 TI_WIZ_REFCLK_DIG>;
> +			assigned-clock-parents = <&k3_clks 405 6>,
> +						 <&k3_clks 405 6>,
> +						 <&k3_clks 405 6>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			#clock-cells = <1>;
> +			status = "disabled";
> +		};
> +	};
> +
> +	serdes_wiz2: wiz@5020000 {
> +		compatible = "ti,j784s4-wiz-10g";
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		power-domains = <&k3_pds 406 TI_SCI_PD_EXCLUSIVE>;
> +		clocks = <&k3_clks 406 2>, <&k3_clks 406 6>, <&serdes_refclk>, <&k3_clks 406 5>;
> +		clock-names = "fck", "core_ref_clk", "ext_ref_clk", "core_ref1_clk";
> +		assigned-clocks = <&k3_clks 406 6>;
> +		assigned-clock-parents = <&k3_clks 406 10>;
> +		num-lanes = <4>;
> +		#reset-cells = <1>;
> +		#clock-cells = <1>;
> +		ranges = <0x05020000 0x00 0x05020000 0x10000>;
> +		status = "disabled";
> +
> +		serdes2: serdes@5020000 {
> +			compatible = "ti,j721e-serdes-10g";
> +			reg = <0x05020000 0x010000>;
> +			reg-names = "torrent_phy";
> +			resets = <&serdes_wiz2 0>;
> +			reset-names = "torrent_reset";
> +			clocks = <&serdes_wiz2 TI_WIZ_PLL0_REFCLK>,
> +				 <&serdes_wiz2 TI_WIZ_PHY_EN_REFCLK>;
> +			clock-names = "refclk", "phy_en_refclk";
> +			assigned-clocks = <&serdes_wiz2 TI_WIZ_PLL0_REFCLK>,
> +					  <&serdes_wiz2 TI_WIZ_PLL1_REFCLK>,
> +					  <&serdes_wiz2 TI_WIZ_REFCLK_DIG>;
> +			assigned-clock-parents = <&k3_clks 406 6>,
> +						 <&k3_clks 406 6>,
> +						 <&k3_clks 406 6>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			#clock-cells = <1>;
> +			status = "disabled";
> +		};
> +	};
> +
> +	serdes_wiz4: wiz@5050000 {
> +		compatible = "ti,j784s4-wiz-10g";
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		power-domains = <&k3_pds 407 TI_SCI_PD_EXCLUSIVE>;
> +		clocks = <&k3_clks 407 2>, <&k3_clks 407 6>, <&serdes_refclk>, <&k3_clks 407 5>;
> +		clock-names = "fck", "core_ref_clk", "ext_ref_clk", "core_ref1_clk";
> +		assigned-clocks = <&k3_clks 407 6>;
> +		assigned-clock-parents = <&k3_clks 407 10>;
> +		num-lanes = <4>;
> +		#reset-cells = <1>;
> +		#clock-cells = <1>;
> +		ranges = <0x05050000 0x00 0x05050000 0x10000>,
> +			 <0xa030a00 0x00 0xa030a00 0x40>; /* DPTX PHY */
> +		status = "disabled";
> +
> +		serdes4: serdes@5050000 {
> +			/*
> +			 * Note: we also map DPTX PHY registers as the Torrent
> +			 * needs to manage those.
> +			 */
> +			compatible = "ti,j721e-serdes-10g";
> +			reg = <0x05050000 0x010000>,
> +			      <0x0a030a00 0x40>; /* DPTX PHY */
> +			reg-names = "torrent_phy";
> +			resets = <&serdes_wiz4 0>;
> +			reset-names = "torrent_reset";
> +			clocks = <&serdes_wiz4 TI_WIZ_PLL0_REFCLK>,
> +				 <&serdes_wiz4 TI_WIZ_PHY_EN_REFCLK>;
> +			clock-names = "refclk", "phy_en_refclk";
> +			assigned-clocks = <&serdes_wiz4 TI_WIZ_PLL0_REFCLK>,
> +					  <&serdes_wiz4 TI_WIZ_PLL1_REFCLK>,
> +					  <&serdes_wiz4 TI_WIZ_REFCLK_DIG>;
> +			assigned-clock-parents = <&k3_clks 407 6>,
> +						 <&k3_clks 407 6>,
> +						 <&k3_clks 407 6>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			#clock-cells = <1>;
> +			status = "disabled";
> +		};
> +	};
> +
>  	main_navss: bus@30000000 {
>  		bootph-all;
>  		compatible = "simple-bus";
> -- 
> 2.25.1
> 

-- 
Regards,
Nishanth Menon
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