Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.36 as permitted sender) client-ip=23.128.96.36;
Message-ID: <8a5d1211-8acb-762d-ae36-bf508b082ef4@intel.com>
Date:   Thu, 28 Sep 2023 08:53:54 -0700
User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101
 Firefox/102.0 Thunderbird/102.15.1
Subject: Re: [PATCH v2 1/4] x86/resctrl: Enable non-contiguous bits in Intel
 CAT
Content-Language: en-US
To:     <babu.moger@amd.com>,
        =?UTF-8?Q?Maciej_Wiecz=c3=b3r-Retman?= 
        <maciej.wieczor-retman@intel.com>
CC:     Fenghua Yu <fenghua.yu@intel.com>,
        Thomas Gleixner <tglx@linutronix.de>,
        Ingo Molnar <mingo@redhat.com>, Borislav Petkov <bp@alien8.de>,
        Dave Hansen <dave.hansen@linux.intel.com>, <x86@kernel.org>,
        "H. Peter Anvin" <hpa@zytor.com>, <linux-kernel@vger.kernel.org>
References: <cover.1695371055.git.maciej.wieczor-retman@intel.com>
 <918e147601697b1d4b8f8589f5751e05d6ceccdf.1695371055.git.maciej.wieczor-retman@intel.com>
 <9751cbaf-8653-d32a-6058-13c251c59b3d@amd.com>
 <4sxjxe4cgvookcobwbrmsoeszjordi3bpjg22zxut3lanjc46j@xpqt6nblx6uc>
 <13b360ac-4292-5056-6d00-6eb1d4186b11@amd.com>
From:   Reinette Chatre <reinette.chatre@intel.com>
In-Reply-To: <13b360ac-4292-5056-6d00-6eb1d4186b11@amd.com>
Content-Type: text/plain; charset="UTF-8"
Content-Transfer-Encoding: 8bit
MIME-Version: 1.0
X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1
X-MS-Exchange-AntiSpam-MessageData-0: =?utf-8?B?RGhTNG41d25Bem92Njh6UHpEZEY1VXcvbU9HWXFicHNKb1VmcXVCTGZVV2I1?=
 =?utf-8?B?UDBvUDJEQVRHTGg4YUFHR3I2MFdHZUJ5eVpXUWUvRkU0TmQ2WkpCcTF4Rnp0?=
 =?utf-8?B?VWZpdDBMTXBPbTBRYTJwRmozQ29SRzFScmgvRWxOZ1hIcnNrRTQ2V0J4L2Fj?=
 =?utf-8?B?OHZVZTJlQ3hjNFBDWFgzVnBTSEJHQ2EzRXlxdFV2UHBtZWkxWjI0OUhwWmE2?=
 =?utf-8?B?dUVHeW55TkZQdkVBL1pPQm9qWS9VTnQveTJRVjlGZzJqN2JvSFRyakVrU1gw?=
 =?utf-8?B?L2VyZFlaVUwyZVhoT3RDemJ1Y1E2WjZZWDBsd3RueTZENTZkdVFFelkzS1Fq?=
 =?utf-8?B?OUhwbytSdkkyZnAyci92SEViQmxhdmgxNWFPMlpwTk5KSGY4cHRWamJDQ1pD?=
 =?utf-8?B?N2JsdURjaDkxS3NJS1hmOXRmamRBU0cvbXV0RnVWK004VWZzUzRMcm9uMGIw?=
 =?utf-8?B?S2VPckJiQVVYSVFIeFh6WlcrTmQ5NXpXbG1hZEpEZVJHT2xjUlB3UkJpUFJZ?=
 =?utf-8?B?VUR5WHQ0NktGVWJCRVpuQ1J2RjVBdDJkT05jUDZPUG9oMzBEOXR5dnovZ1Bw?=
 =?utf-8?B?b3g1ak1KMXVSalZZT1pHZ3lZZnZZNTJIVHJ3b2tLUTk1MVh2Umg3L1V1VUxQ?=
 =?utf-8?B?YzRWNVNnTmRNNFRNaW44WDgrVG91Wm5YOVh4VnR4Zy9ya1ZuRjFxdi92RE5G?=
 =?utf-8?B?QTEyOVg4S0RjUmp1eWtrSE5LK1c5TDQwbXpERmk1Z2pZUjZINFhoeXYxOHBn?=
 =?utf-8?B?ejh6YVBtOEZTWDIyNmtlbDhpS2VWMzY1bFVPcDNzZnZ6K3lzUnNSd3JZYTNB?=
 =?utf-8?B?UU8wS1JHZEUwSThZVHFWdUxnM0dxald2Nmlpd2hwVHBtL2ZOdmZYZ2FZempZ?=
 =?utf-8?B?djgrY2RneGNhM1F3Qm5Db3JsR0hudVpwbzRwL0haTlNrUEJDb3krWGlnczFW?=
 =?utf-8?B?U1pjZlFnZkhrVXo3TmQ3bjFMeWphRnNzalNPa3dQdmk2THh1bG94VVoxYjFJ?=
 =?utf-8?B?VGdsWTl3aHZZNHoyTUk0OUZDdFdEY0ZIdUUvSENWWGo1Nkx5QklaWTdrMEFo?=
 =?utf-8?B?a3pSRnlobzBWQjg3Vis2T1U1anpSeXgvRElzQUpmWWl4aUt2Ukl3VEsxMHBs?=
 =?utf-8?B?QTZCcW1VYmpVNm1zN2lURXAxc3NKK1M3ckQ4a3kvV2lvWUY3c2xUSjhBbXMr?=
 =?utf-8?B?WU44NklYOU4vNGErSGQyZXJjQlVOMUVyNjZGUzZJV0dHeWVSbDB6S0RxcWFM?=
 =?utf-8?B?am9WWFpXckoyUm9vNVpqc1pVdG1TV1lyV0QyL2xBaWJNblh2dkg1RmE2Wm9l?=
 =?utf-8?B?UG9iZG9nYVNhOE5zSWRaVGhpMnVmaU4zaU5nRFFkaHNabko4OVJ5bFcvMXM3?=
 =?utf-8?B?RUJER25EQXZNSUxubXI4ZE9qaFA3YXk3QmczSmpuYXRrOFVUR3lqdi8wNy9j?=
 =?utf-8?B?TVRZcGdITHNDQ1c3VHM0cHJXNGxWTUpGeHFJL01WWnBISnFJZUJtRi9yVWE3?=
 =?utf-8?B?aGJZWW5aaXZxY0tVRHg2cXVUR1FJUjEzZDUvdXdhUE12VU13ZzY4cWV3RnJp?=
 =?utf-8?B?VHBjYzcyTHJrVWtMb1lEbXlHZU9TZ2hCMkRFdU1Idk90SWYvMW5oa0RHcmhk?=
 =?utf-8?B?NFFoY29tK096b2pyTFRkeDJ3cm1aVUZ5czM2aktpcW1VZk9NcGViYW9jZkw5?=
 =?utf-8?B?TXc4RW5yMTlBWjM4Kzd4OUttS0Rvc2hLaHlQeEVzSUp3TmdYdTJHU0IyRllo?=
 =?utf-8?B?NHg0T2VmMjRDNTFOTkptbjZVTWZ0MFVRL2pTYWR6NnRCcS9nL1RIK2RsM1RU?=
 =?utf-8?B?TXNJWUtldDBRZVovemloVzVOdVphb3orSHNEOUxyQUJoNEFXdnhCRTdwS1Fy?=
 =?utf-8?B?V3Q2c1ZHOGNBQm1PTWdIUUNoRFBuaHNwbFdBS1dFZERaZ0lxSmEvUmlzZTIy?=
 =?utf-8?B?K09nYkQwUnpoL1FTK3JRVEhQMnZsR29zQXA2ejRNZWx1UWxmL1EzNWozc0o5?=
 =?utf-8?B?NVJaODQ1OTArL3Rsd0ZHS3d2UnhuM3AvalY1RkI2Q3pQTlYrdDdPeHNYRVlD?=
 =?utf-8?B?dlVaWVArMHh6Mmx3TTlEWUxpNEUvTDliczdoeXVOTFFUWmRPNnkxU252WFdV?=
 =?utf-8?B?czhybExvc0FaY3BXRWtteUFpUmF2UHpjU2lTTFlMY1JESndQdXBVSm5xWW15?=
 =?utf-8?B?cUE9PQ==?=
X-MS-Exchange-CrossTenant-Network-Message-Id: ffe572af-ee60-4fa5-13b0-08dbc03b200f
X-MS-Exchange-CrossTenant-AuthSource: SJ2PR11MB7573.namprd11.prod.outlook.com
X-MS-Exchange-CrossTenant-AuthAs: Internal
X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Sep 2023 15:53:57.7868
 (UTC)
X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted
X-MS-Exchange-CrossTenant-Id: 46c98d88-e344-4ed4-8496-4ed7712e255d
X-MS-Exchange-CrossTenant-MailboxType: HOSTED
X-MS-Exchange-CrossTenant-UserPrincipalName: vjV/koeR/K+WoTUurxStVI6krYYpgdt1RUg7kGct+jKe7F3CMrkCIGdDzesxL138qjD0CdhwT1d/IcEeH6Ozpg7XrdpA1/xtZfBIXuJaL6k=
X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR11MB6775
X-OriginatorOrg: intel.com
X-Spam-Status: No, score=-2.3 required=5.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED,
	DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,
	MAILING_LIST_MULTI,NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS
	autolearn=unavailable autolearn_force=no version=3.4.6
X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on pete.vger.email
Precedence: bulk
List-ID: <linux-kernel.vger.kernel.org>
X-Mailing-List: linux-kernel@vger.kernel.org
X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (pete.vger.email [0.0.0.0]); Thu, 28 Sep 2023 08:54:34 -0700 (PDT)

Hi Babu,

On 9/28/2023 8:08 AM, Moger, Babu wrote:
> On 9/28/23 02:06, Maciej Wieczór-Retman wrote:
>> On 2023-09-27 at 17:34:27 -0500, Moger, Babu wrote:
>>> On 9/22/2023 3:48 AM, Maciej Wieczor-Retman wrote:
...

>>>> diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resctrl/core.c
>>>> index 030d3b409768..c783a873147c 100644
>>>> --- a/arch/x86/kernel/cpu/resctrl/core.c
>>>> +++ b/arch/x86/kernel/cpu/resctrl/core.c
>>>> @@ -152,6 +152,7 @@ static inline void cache_alloc_hsw_probe(void)
>>>>   	r->cache.cbm_len = 20;
>>>>   	r->cache.shareable_bits = 0xc0000;
>>>>   	r->cache.min_cbm_bits = 2;
>>>> +	r->cache.arch_has_sparse_bitmaps = false;
>>>
>>> Is this change required?
>>>
>>> This is always set to false in rdt_init_res_defs_intel().
>>
>> The logic behind moving this variable initialization from
>> rdt_init_res_defs_intel() into both cache_alloc_hsw_probe() and
>> rdt_get_cache_alloc_cfg() is that the variable doesn't really have a
>> default value anymore. It used to when the CPUID.0x10.1:ECX[3] and
>> CPUID.0x10.2:ECX[3] bits were reserved.
>>
>> Now for the general case the variable is dependent on CPUID output.
>> And only for Haswell case it needs to be hardcoded to "false", so the
>> assignment makes more sense in Haswell probe rather than in the default
>> section.
> 
> Here is the current sequence order with your change.
> 
> 1.
> resctrl_late_init -> check_quirks -> __check_quirks_intel ->
> cache_alloc_hsw_probe
>    r->cache.arch_has_sparse_bitmaps = false; (new code)
> 
> 2. resctrl_late_init -> rdt_init_res_defs -> rdt_init_res_defs_intel
>    r->cache.arch_has_sparse_bitmaps = false; (old code)
> 
> 3. resctrl_late_init -> get_rdt_resources -> get_rdt_alloc_resources ->
> rdt_get_cache_alloc_cfg
>    r->cache.arch_has_sparse_bitmaps = ecx.split.noncont; (new code)
> 
> The code in (3) is going to overwrite whatever is set in (1) or (2).
> 
> I would say you can just remove initialization in both (1) and (2). That
> makes the code clearer to me. I assume reserved bits in Intel is always 0.
> 

I believe Maciej already addressed this in his response to a similar question
from Peter. Please see:
https://lore.kernel.org/lkml/xnjmmsj5pjskbqeynor2ztha5dmkhxa44j764ohtjhtywy7idb@soobjiql4liy/

Reinette