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Message-ID: <f3eba136-74d4-4f54-b35d-ce3236db9f67@quicinc.com>
Date:   Wed, 27 Sep 2023 17:42:25 +0530
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Subject: Re: [PATCH v2 08/11] arm64: dts: qcom: ipq8074: include the GPLL0 as
 clock provider for mailbox
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To:     Konrad Dybcio <konrad.dybcio@linaro.org>,
        Andy Gross <agross@kernel.org>,
        Bjorn Andersson <andersson@kernel.org>,
        Michael Turquette <mturquette@baylibre.com>,
        Stephen Boyd <sboyd@kernel.org>,
        "Sricharan Ramabadhran" <quic_srichara@quicinc.com>,
        Gokul Sriram Palanisamy <quic_gokulsri@quicinc.com>,
        Varadarajan Narayanan <quic_varada@quicinc.com>,
        Anusha Rao <quic_anusha@quicinc.com>,
        Devi Priya <quic_devipriy@quicinc.com>,
        Jassi Brar <jassisinghbrar@gmail.com>,
        Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Conor Dooley <conor+dt@kernel.org>
CC:     <linux-arm-msm@vger.kernel.org>, <linux-clk@vger.kernel.org>,
        <linux-kernel@vger.kernel.org>, <devicetree@vger.kernel.org>
References: <20230913-gpll_cleanup-v2-0-c8ceb1a37680@quicinc.com>
 <20230913-gpll_cleanup-v2-8-c8ceb1a37680@quicinc.com>
 <731f4e05-6205-432b-8cd5-29d5e1c2222d@linaro.org>
From:   Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
In-Reply-To: <731f4e05-6205-432b-8cd5-29d5e1c2222d@linaro.org>
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On 9/27/2023 5:03 PM, Konrad Dybcio wrote:
> On 14.09.2023 08:59, Kathiravan Thirumoorthy wrote:
>> While the kernel is booting up, APSS PLL will be running at 800MHz with
>> GPLL0 as source. Once the cpufreq driver is available, APSS PLL will be
>> configured to the rate based on the opp table and the source also will
>> be changed to APSS_PLL_EARLY. So allow the mailbox to consume the GPLL0,
>> with this inclusion, CPU Freq correctly reports that CPU is running at
>> 800MHz rather than 24MHz.
>>
>> Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
>> ---
> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
>
> Konrad

Thanks Konrad.

I just realized that, in commit message, the statement "APSS PLL will be 
running at 800MHz" should be "APSS clock / CPU clock will be running at 
800MHz".

Bjorn, will you be able to fix it up while applying (all 4 DTS changes 
needs update) or shall I respin it?

Thanks,

Kathiravan T.