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Subject: Re: [PATCH] clk: qcom: gcc-sm8150: Fix gcc_sdcc2_apps_clk_src
From:   Stephen Boyd <sboyd@kernel.org>
Cc:     adomerlee@gmail.com, linux-arm-msm@vger.kernel.org,
        linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org
To:     Danila Tikhonov <danila@jiaxyga.com>,
        Konrad Dybcio <konrad.dybcio@linaro.org>, agross@kernel.org,
        andersson@kernel.org, dkatraga@codeaurora.org,
        mturquette@baylibre.com, quic_tdas@quicinc.com, vkoul@kernel.org
Date:   Thu, 28 Sep 2023 16:53:19 -0700
User-Agent: alot/0.10
Precedence: bulk

Quoting Konrad Dybcio (2023-09-15 05:04:41)
> On 14.09.2023 18:20, Stephen Boyd wrote:
> > Quoting Danila Tikhonov (2023-09-13 10:56:11)
> >> Set .flags =3D CLK_OPS_PARENT_ENABLE to fix "gcc_sdcc2_apps_clk_src: r=
cg
> >> didn't update its configuration" error.
> >>
> >> Fixes: 2a1d7eb854bb ("clk: qcom: gcc: Add global clock controller driv=
er for SM8150")
> >> Tested-by: Arseniy Velikanov <adomerlee@gmail.com>
> >> Signed-off-by: Danila Tikhonov <danila@jiaxyga.com>
> >> ---
> >>  drivers/clk/qcom/gcc-sm8150.c | 2 +-
> >>  1 file changed, 1 insertion(+), 1 deletion(-)
> >>
> >> diff --git a/drivers/clk/qcom/gcc-sm8150.c b/drivers/clk/qcom/gcc-sm81=
50.c
> >> index 41ab210875fb..05d115c52dfe 100644
> >> --- a/drivers/clk/qcom/gcc-sm8150.c
> >> +++ b/drivers/clk/qcom/gcc-sm8150.c
> >> @@ -774,7 +774,7 @@ static struct clk_rcg2 gcc_sdcc2_apps_clk_src =3D {
> >>                 .name =3D "gcc_sdcc2_apps_clk_src",
> >>                 .parent_data =3D gcc_parents_6,
> >>                 .num_parents =3D ARRAY_SIZE(gcc_parents_6),
> >> -               .flags =3D CLK_SET_RATE_PARENT,
> >> +               .flags =3D CLK_OPS_PARENT_ENABLE,
> >>                 .ops =3D &clk_rcg2_floor_ops,
> >=20
> > In what case are we getting the rcg stuck? I thought that you could
> > write the rcg registers while the parent was off and switch to that
> > parent if the parent isn't enabled and it wouldn't get stuck.
> I think the better question here would be "why isn't
> OPS_PARENT_ENABLE the default for all qc clocks on all
> platforms" :/
>=20

We don't need that flag because of how the hardware works and how the
clk framework moves the enable of the parent from the old parent to the
new parent when changing rates. The RCGs only get stuck if we change the
parent of an RCG to a disabled parent when the current parent is enabled
and the RCG is enabled. Otherwise we're free to change the parent of the
RCG because it isn't trying to do a glitch free switch of clk frequency.

Is it possible that the clk is running out of boot on a parent that
is enabled in the hardware but doesn't look enabled to the clk framework
because of how we fail to hand off enable state? Maybe the mmc driver
then calls clk_set_rate() to change the rate (rcg is still off) and that
causes problems?