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Subject: Sony IMX290/462 image sensors I2C xfer peculiarity
Date:   Fri, 29 Sep 2023 12:53:21 +0200
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Hi,

I am debugging certain IMX290 and IMX462 I2C failures on an NXP
i.MX6MP based board and there seem to be interesting "feature" here:
Sony IMX290 and IMX462 image sensors apparently terminate I2C transfers
after 2^18 of their master clock cycles. For example, with a typical
37.125 MHz clock oscillator, this means about 7 ms. In practice, I'm
barely able to read a block of 128 registers (at I2C 400 kHz clock
rate).

I think the sensors simply disconnect from the bus after 2^18 clock
cycles (starting from the first START condition, the repeated STARTs
don't reset the timeout). This means, in case of a READ operation, the
data read by the CPU after the timeout contains all bits set to 1.
i.MX8MP detects arbitration losses, so if the SDA change to 1 happens on
high clock value (but not on ACK bit), the whole transfer is aborted.
Otherwise, the ending bytes are simply set to FF (and the last non-FF
may be corrupted partially).

The problem is 7 ms is a short time and on a non-real time system even
a simple non-DMA I2C register writes can take as much time. This causes
driver failures.

Needless to say, the datasheets know nothing about the feature.

Any thoughts?
--=20
Krzysztof "Chris" Ha=C5=82asa

Sie=C4=87 Badawcza =C5=81ukasiewicz
Przemys=C5=82owy Instytut Automatyki i Pomiar=C3=B3w PIAP
Al. Jerozolimskie 202, 02-486 Warszawa