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From:   "Lad, Prabhakar" <prabhakar.csengg@gmail.com>
Date:   Fri, 29 Sep 2023 15:45:53 +0100
Message-ID: <CA+V-a8sXxzUPmV5LqGtYm2SYLHS+-VNo_jRsLNP4mUSAKxuoFw@mail.gmail.com>
Subject: Re: [PATCH 5/5] riscv: configs: defconfig: Enable configs required
 for RZ/Five SoC
To:     Conor Dooley <conor@kernel.org>
Cc:     Geert Uytterhoeven <geert+renesas@glider.be>,
        Magnus Damm <magnus.damm@gmail.com>,
        Conor Dooley <conor+dt@kernel.org>,
        Paul Walmsley <paul.walmsley@sifive.com>,
        Palmer Dabbelt <palmer@dabbelt.com>,
        Albert Ou <aou@eecs.berkeley.edu>,
        Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org,
        linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
        Biju Das <biju.das.jz@bp.renesas.com>,
        Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
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Hi Conor,

Thank  you for review.

On Fri, Sep 29, 2023 at 3:14=E2=80=AFPM Conor Dooley <conor@kernel.org> wro=
te:
>
> On Fri, Sep 29, 2023 at 01:07:04AM +0100, Prabhakar wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > Enable the configs required by the below IP blocks which are
> > present on RZ/Five SoC:
> > * ADC
> > * CANFD
> > * DMAC
> > * eMMC/SDHI
> > * OSTM
> > * RAVB (+ Micrel PHY)
> > * RIIC
> > * RSPI
> > * SSI (Sound+WM8978 codec)
> > * Thermal
> > * USB (PHY/RESET/OTG)
> >
> > Along with the above some core configs are enabled too,
> > -> CPU frequency scaling as RZ/Five does support this.
> > -> MTD is enabled as RSPI can be connected to flash chips
> > -> Enabled I2C chardev so that it enables userspace to read/write
> >    i2c devices (similar to arm64)
> > -> Thermal configs as RZ/Five SoC does have thermal unit
> > -> GPIO regulator as we might have IP blocks for which voltage
> >    levels are controlled by GPIOs
>
> You might or you do?
>
Yes we do use the gpio regulator for SDHI.

Cheers,
Prabhakar