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[188.141.3.169]) by smtp.gmail.com with ESMTPSA id 11-20020a05600c020b00b003fe2b081661sm3408261wmi.30.2023.09.30.06.41.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Sep 2023 06:41:20 -0700 (PDT) From: Bryan O'Donoghue To: andersson@kernel.org, agross@kernel.org, konrad.dybcio@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, jonathan@marek.ca, quic_tdas@quicinc.com, vladimir.zapolskiy@linaro.org Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, bryan.odonoghue@linaro.org Subject: [PATCH v2 2/5] dt-bindings: clock: Add SM8550 CAMCC yaml Date: Sat, 30 Sep 2023 14:41:11 +0100 Message-Id: <20230930134114.1816590-3-bryan.odonoghue@linaro.org> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230930134114.1816590-1-bryan.odonoghue@linaro.org> References: <20230930134114.1816590-1-bryan.odonoghue@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (howler.vger.email [0.0.0.0]); Sat, 30 Sep 2023 06:41:35 -0700 (PDT) The SM8550 should have its own yaml description file, not be listed as a compatible string of the SM8450 CAMCC driver since SM8450 and SM8550 have separate CAMCC drivers. Signed-off-by: Bryan O'Donoghue --- .../bindings/clock/qcom,sm8450-camcc.yaml | 8 +-- .../bindings/clock/qcom,sm8550-camcc.yaml | 56 +++++++++++++++++++ 2 files changed, 58 insertions(+), 6 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/qcom,sm8550-camcc.yaml diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml index 5db7bd8424d8..9d16acc53312 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml @@ -13,18 +13,14 @@ description: | Qualcomm camera clock control module provides the clocks, resets and power domains on SM8450. - See also:: - include/dt-bindings/clock/qcom,sm8450-camcc.h - include/dt-bindings/clock/qcom,sm8550-camcc.h + See also:: include/dt-bindings/clock/qcom,sm8450-camcc.h allOf: - $ref: qcom,camcc-common.yaml# properties: compatible: - enum: - - qcom,sm8450-camcc - - qcom,sm8550-camcc + const: qcom,sm8450-camcc clocks: items: diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8550-camcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8550-camcc.yaml new file mode 100644 index 000000000000..93534632c0a2 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,sm8550-camcc.yaml @@ -0,0 +1,56 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sm8550-camcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Camera Clock & Reset Controller on SM8550 + +maintainers: + - Bryan O'Donoghue + +description: | + Qualcomm camera clock control module provides the clocks, resets and power + domains on SM8550. + + See also:: include/dt-bindings/clock/qcom,sm8550-camcc.h + +allOf: + - $ref: qcom,camcc-common.yaml# + +properties: + compatible: + const: qcom,sm8550-camcc + + clocks: + items: + - description: Camera AHB clock from GCC + - description: Board XO source + - description: Board active XO source + - description: Sleep clock source + +required: + - power-domains + - required-opps + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + clock-controller@ade0000 { + compatible = "qcom,sm8550-camcc"; + reg = <0xade0000 0x20000>; + clocks = <&gcc GCC_CAMERA_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>; + power-domains = <&rpmhpd RPMHPD_MMCX>; + required-opps = <&rpmhpd_opp_low_svs>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +... -- 2.40.1