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Date:   Mon, 2 Oct 2023 14:35:27 +0200
From:   Miquel Raynal <miquel.raynal@bootlin.com>
To:     dregan@mail.com
Cc:     bcm-kernel-feedback-list@broadcom.com,
        linux-mtd@lists.infradead.org, f.fainelli@gmail.com,
        rafal@milecki.pl, joel.peshkin@broadcom.com,
        computersforpeace@gmail.com, dan.beygelman@broadcom.com,
        william.zhang@broadcom.com, frieder.schrempf@kontron.de,
        linux-kernel@vger.kernel.org, vigneshr@ti.com, richard@nod.at,
        bbrezillon@kernel.org, kdasu.kdev@gmail.com
Subject: Re: [PATCH v2] mtd: rawnand: brcmnand: Initial exec_op
 implementation
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Hi David,

dregan@mail.com wrote on Sat, 30 Sep 2023 03:57:35 +0200:

> Initial exec_op implementation for Broadcom STB, Broadband and iProc SoC
> This adds exec_op and removes the legacy interface.
>=20
> Signed-off-by: David Regan <dregan@mail.com>
> Reviewed-by: William Zhang <william.zhang@broadcom.com>
>=20
> ---
>=20

...

> +static int brcmnand_parser_exec_matched_op(struct nand_chip *chip,
> +					 const struct nand_subop *subop)
> +{
> +	struct brcmnand_host *host =3D nand_get_controller_data(chip);
> +	struct brcmnand_controller *ctrl =3D host->ctrl;
> +	struct mtd_info *mtd =3D nand_to_mtd(chip);
> +	const struct nand_op_instr *instr =3D &subop->instrs[0];
> +	unsigned int i;
> +	int ret =3D 0;
> +
> +	for (i =3D 0; i < subop->ninstrs; i++) {
> +		instr =3D &subop->instrs[i];
> +
> +		if ((instr->type =3D=3D NAND_OP_CMD_INSTR) &&
> +			(instr->ctx.cmd.opcode =3D=3D NAND_CMD_STATUS))
> +			ctrl->status_cmd =3D 1;
> +		else if (ctrl->status_cmd && (instr->type =3D=3D NAND_OP_DATA_IN_INSTR=
)) {
> +			/*
> +			 * need to fake the nand device write protect because nand_base does a
> +			 * nand_check_wp which calls nand_status_op NAND_CMD_STATUS which che=
cks
> +			 * that the nand is not write protected before an operation starts.
> +			 * The problem with this is it's done outside exec_op so the nand is
> +			 * write protected and this check will fail until the write or erase
> +			 * or write back operation actually happens where we turn off wp.
> +			 */
> +			u8 *in;
> +
> +			ctrl->status_cmd =3D 0;
> +
> +			instr =3D &subop->instrs[i];
> +			in =3D instr->ctx.data.buf.in;
> +			in[0] =3D brcmnand_status(host) | NAND_STATUS_WP; /* hide WP status */

I don't understand why you are faking the WP bit. If it's set,
brcmnand_status() should return it and you should not care about it. If
it's not however, can you please give me the path used when we have
this issue? Either we need to modify the core or we need to provide
additional helpers in this driver to circumvent the faulty path.

> +		} else if (instr->type =3D=3D NAND_OP_WAITRDY_INSTR) {
> +			ret =3D bcmnand_ctrl_poll_status(host, NAND_CTRL_RDY, NAND_CTRL_RDY, =
0);
> +			if (ctrl->wp_cmd) {
> +				ctrl->wp_cmd =3D 0;
> +				brcmnand_wp(mtd, 1);

This ideally should disappear.

> +			}
> +		} else { /* otherwise pass to low level implementation */
> +			if ((instr->type =3D=3D NAND_OP_CMD_INSTR) &&
> +				(instr->ctx.cmd.opcode =3D=3D NAND_CMD_RESET)) {
> +				brcmnand_status(host);
> +				ctrl->status_cmd =3D 0;
> +				ctrl->wp_cmd =3D 0;
> +				brcmnand_wp(mtd, 1);

Same

> +			}
> +
> +			if ((instr->type =3D=3D NAND_OP_CMD_INSTR) &&
> +				((instr->ctx.cmd.opcode =3D=3D NAND_CMD_ERASE1) ||
> +				(instr->ctx.cmd.opcode =3D=3D NAND_CMD_SEQIN))) {
> +				brcmnand_wp(mtd, 0);
> +				ctrl->wp_cmd =3D 1;

Same

> +			}
> +
> +			ret =3D brcmnand_exec_instr(host, instr, i =3D=3D (subop->ninstrs - 1=
));
> +		}
> +	}
> +
> +	return ret;
> +}


Thanks,
Miqu=C3=A8l