Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.34 as permitted sender) client-ip=23.128.96.34;
Date:   Mon, 2 Oct 2023 15:46:28 +0100
From:   Jonathan Cameron <Jonathan.Cameron@Huawei.com>
To:     Robert Richter <rrichter@amd.com>
CC:     Alison Schofield <alison.schofield@intel.com>,
        Vishal Verma <vishal.l.verma@intel.com>,
        Ira Weiny <ira.weiny@intel.com>,
        Ben Widawsky <bwidawsk@kernel.org>,
        Dan Williams <dan.j.williams@intel.com>,
        "Davidlohr Bueso" <dave@stgolabs.net>,
        Dave Jiang <dave.jiang@intel.com>, <linux-cxl@vger.kernel.org>,
        <linux-kernel@vger.kernel.org>,
        Bjorn Helgaas <bhelgaas@google.com>,
        Terry Bowman <terry.bowman@amd.com>
Subject: Re: [PATCH v11 10/20] cxl/pci: Introduce config option PCIEAER_CXL
Message-ID: <20231002154628.00004f9b@Huawei.com>
In-Reply-To: <20230927154339.1600738-11-rrichter@amd.com>
References: <20230927154339.1600738-1-rrichter@amd.com>
        <20230927154339.1600738-11-rrichter@amd.com>
Organization: Huawei Technologies Research and Development (UK) Ltd.
MIME-Version: 1.0
Content-Type: text/plain; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
Precedence: bulk

On Wed, 27 Sep 2023 17:43:29 +0200
Robert Richter <rrichter@amd.com> wrote:

> CXL error handling depends on AER.
> 
> Introduce config option PCIEAER_CXL in preparation of the AER dport
> error handling. Also, introduce the stub function
> devm_cxl_setup_parent_dport() to setup dports.
> 
> This is in preparation of follow on patches.
> 
> Note the Kconfg part of the option is added in a later patch to enable
> it once coding of the feature is complete.
> 
> Signed-off-by: Robert Richter <rrichter@amd.com>

Feels like it should just be combined with a later patch that fills
some of this in as on it's own it's just a weird snippet of code :)

Still, one comment inline anyway.


> ---
>  drivers/cxl/core/pci.c | 9 +++++++++
>  drivers/cxl/cxl.h      | 7 +++++++
>  drivers/cxl/mem.c      | 2 ++
>  3 files changed, 18 insertions(+)
> 
> diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c
> index c7a7887ebdcf..6ba3b7370816 100644
> --- a/drivers/cxl/core/pci.c
> +++ b/drivers/cxl/core/pci.c
> @@ -718,6 +718,15 @@ static bool cxl_report_and_clear(struct cxl_dev_state *cxlds)
>  	return true;
>  }
>  
> +#ifdef CONFIG_PCIEAER_CXL
> +
> +void devm_cxl_setup_parent_dport(struct device *host, struct cxl_dport *dport)
> +{
> +}
> +EXPORT_SYMBOL_NS_GPL(devm_cxl_setup_parent_dport, CXL);
> +
> +#endif
> +
>  pci_ers_result_t cxl_error_detected(struct pci_dev *pdev,
>  				    pci_channel_state_t state)
>  {
> diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
> index c07064e0c136..cfa2f6bede41 100644
> --- a/drivers/cxl/cxl.h
> +++ b/drivers/cxl/cxl.h
> @@ -704,6 +704,13 @@ struct cxl_dport *devm_cxl_add_rch_dport(struct cxl_port *port,
>  					 struct device *dport_dev, int port_id,
>  					 resource_size_t rcrb);
>  
> +#ifdef CONFIG_PCIEAER_CXL
> +void devm_cxl_setup_parent_dport(struct device *host, struct cxl_dport *dport);
> +#else
> +static inline void devm_cxl_setup_parent_dport(struct device *host,
> +					       struct cxl_dport *dport) { }
> +#endif
> +
>  struct cxl_decoder *to_cxl_decoder(struct device *dev);
>  struct cxl_root_decoder *to_cxl_root_decoder(struct device *dev);
>  struct cxl_switch_decoder *to_cxl_switch_decoder(struct device *dev);
> diff --git a/drivers/cxl/mem.c b/drivers/cxl/mem.c
> index 04107058739b..61ca21c020fa 100644
> --- a/drivers/cxl/mem.c
> +++ b/drivers/cxl/mem.c
> @@ -157,6 +157,8 @@ static int cxl_mem_probe(struct device *dev)
>  	else
>  		endpoint_parent = &parent_port->dev;
>  
> +	devm_cxl_setup_parent_dport(dev, dport);

devm calls can always fail (because if nothing else you have to register
some cleanup and that involves an allocation.  If you want to ignore
that I'd expect a comment here.

> +
>  	device_lock(endpoint_parent);
>  	if (!endpoint_parent->driver) {
>  		dev_err(dev, "CXL port topology %s not enabled\n",