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Date:   Mon, 2 Oct 2023 15:49:43 +0200
From:   Miquel Raynal <miquel.raynal@bootlin.com>
To:     Martin =?UTF-8?B?SHVuZGViw7hsbA==?= <martin@geanix.com>
Cc:     Rouven Czerwinski <r.czerwinski@pengutronix.de>,
        =?UTF-8?B?TcOlbnMg?= =?UTF-8?B?UnVsbGfDpXJk?= <mans@mansr.com>,
        Alexander Shiyan <eagle.alexander923@gmail.com>,
        Richard Weinberger <richard@nod.at>,
        Vignesh Raghavendra <vigneshr@ti.com>,
        JaimeLiao <jaimeliao.tw@gmail.com>, kernel@pengutronix.de,
        stable@vger.kernel.org, linux-mtd@lists.infradead.org,
        linux-kernel@vger.kernel.org,
        Sean =?UTF-8?B?Tnlla2rDpnI=?= <sean@geanix.com>,
        Domenico Punzo <dpunzo@micron.com>,
        Bean Huo <beanhuo@micron.com>
Subject: Re: [PATCH v2] mtd: rawnand: Ensure the nand chip supports cached
 reads
Message-ID: <20231002154943.361e31b0@xps-13>
In-Reply-To: <b8de26e243afa3e5920455a4d8e5a3451a06d074.camel@geanix.com>
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        <e911f5d9c7def8c80904a17ad3924ecba6625998.camel@geanix.com>
        <20230926132725.5d570e1b@xps-13>
        <20230927170516.2604e8f2@xps-13>
        <b8de26e243afa3e5920455a4d8e5a3451a06d074.camel@geanix.com>
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Hi Martin,

martin@geanix.com wrote on Thu, 28 Sep 2023 09:19:56 +0200:

> Hi Miquel,
>=20
> On Wed, 2023-09-27 at 17:05 +0200, Miquel Raynal wrote:
> > Hi Martin,
> >=20
> > miquel.raynal@bootlin.com=C2=A0wrote on Tue, 26 Sep 2023 13:27:25 +0200:
> >  =20
> > > Hi Martin,
> > >=20
> > > + Bean and Domenico, there is a question for you below.
> > >=20
> > > martin@geanix.com=C2=A0wrote on Mon, 25 Sep 2023 13:01:06 +0200:
> > >  =20
> > > > Hi Rouven,
> > > >=20
> > > > On Fri, 2023-09-22 at 16:17 +0200, Rouven Czerwinski wrote:=C2=A0  =
=20
> > > > > Both the JEDEC and ONFI specification say that read cache
> > > > > sequential
> > > > > support is an optional command. This means that we not only
> > > > > need to
> > > > > check whether the individual controller supports the command,
> > > > > we also
> > > > > need to check the parameter pages for both ONFI and JEDEC NAND
> > > > > flashes
> > > > > before enabling sequential cache reads.
> > > > >=20
> > > > > This fixes support for NAND flashes which don't support
> > > > > enabling
> > > > > cache
> > > > > reads, i.e. Samsung K9F4G08U0F or Toshiba TC58NVG0S3HTA00.
> > > > >=20
> > > > > Sequential cache reads are now only available for ONFI and
> > > > > JEDEC
> > > > > devices, if individual vendors implement this, it needs to be
> > > > > enabled
> > > > > per vendor.
> > > > >=20
> > > > > Tested on i.MX6Q with a Samsung NAND flash chip that doesn't
> > > > > support
> > > > > sequential reads.
> > > > >=20
> > > > > Fixes: 003fe4b9545b ("mtd: rawnand: Support for sequential
> > > > > cache
> > > > > reads")
> > > > > Cc: stable@vger.kernel.org
> > > > > Signed-off-by: Rouven Czerwinski
> > > > > <r.czerwinski@pengutronix.de>=C2=A0=C2=A0=C2=A0  =20
> > > >=20
> > > > Thanks for this. It works as expected for my Toshiba chip,
> > > > obviously
> > > > because it doesn't use ONFI or JEDEC.
> > > >=20
> > > > Unfortunately, my Micron chip does use ONFI, and it sets the
> > > > cached-
> > > > read-supported bit. It then fails when reading afterwords: =20
> >=20
> > I might have over reacted regarding my findings in Micron's
> > datasheet,
> > I need to know if you use the on-die ECC engine or if you use the one
> > on the controller. In the former case the failure is expected. In the
> > latter case, it's not. =20
>=20
> I use the default, which seems to be the controller engine?

Yeah, you're using the gpmi NAND controller right? If that's the case,
it seems that only ECC correction is supported.

Thanks,
Miqu=C3=A8l