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Tue, 03 Oct 2023 08:04:31 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 39384UjL025473 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 3 Oct 2023 08:04:30 GMT Received: from [10.214.66.58] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.36; Tue, 3 Oct 2023 01:04:26 -0700 Message-ID: <5d99708e-95a0-401b-b636-4f535fdd5905@quicinc.com> Date: Tue, 3 Oct 2023 13:34:23 +0530 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 1/3] arm64: dts: qcom: Add interconnect nodes for SDX75 To: Konrad Dybcio , , , , , , CC: , , References: <1695720564-2978-1-git-send-email-quic_rohiagar@quicinc.com> <1695720564-2978-2-git-send-email-quic_rohiagar@quicinc.com> <35703a29-5c5a-47a8-9a4b-04953dc3faba@linaro.org> Content-Language: en-US From: Rohit Agarwal In-Reply-To: <35703a29-5c5a-47a8-9a4b-04953dc3faba@linaro.org> Content-Type: text/plain; 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Tue, 03 Oct 2023 01:04:54 -0700 (PDT) On 9/27/2023 4:17 PM, Konrad Dybcio wrote: > On 26.09.2023 11:29, Rohit Agarwal wrote: >> Add interconnect nodes to support interconnects on SDX75. >> Also parallely add the interconnect property for UART required >> so that the bootup to shell does not break with interconnects >> in place. >> >> Signed-off-by: Rohit Agarwal >> --- > [...] > >> scm: scm { >> compatible = "qcom,scm-sdx75", "qcom,scm"; >> @@ -434,6 +448,8 @@ >> clock-names = "m-ahb", >> "s-ahb"; >> iommus = <&apps_smmu 0xe3 0x0>; >> + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>; > 0 -> QCOM_ICC_TAG_ALWAYS (dt-bindings/interconnect/qcom,icc.h) Ok, Let me update this. Thanks, Rohit. > > Konrad