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[23.128.96.33]) by mx.google.com with ESMTPS id fa19-20020a056a002d1300b0068fa8499af1si1265075pfb.11.2023.10.03.04.04.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Oct 2023 04:04:43 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.33 as permitted sender) client-ip=23.128.96.33; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=bbQmSSM4; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.33 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by lipwig.vger.email (Postfix) with ESMTP id 9DF75802EEE2; Tue, 3 Oct 2023 04:04:41 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at lipwig.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239999AbjJCLEU (ORCPT + 99 others); Tue, 3 Oct 2023 07:04:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50724 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240000AbjJCLES (ORCPT ); Tue, 3 Oct 2023 07:04:18 -0400 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 139BAD7; Tue, 3 Oct 2023 04:04:15 -0700 (PDT) Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 393B43MP060583; Tue, 3 Oct 2023 06:04:03 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1696331043; bh=iYebNZPy/CKbXWaKFyAsuXzDusEsLM6uFiE/1hHDe00=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=bbQmSSM4pfLvDFexR7d7Ubk3ALBFl4q/H8cFIUufS5s1aCc8WSpFNifmvJFrTa830 /W4lupXzRJfaXRo+lv3PGwl3wgKc0idELhyzYHvpaYFaqf2qh6kqohy8zL6a6p1Q3S oiwcPCEsILZaDtPvKyIi5NwMs8pdcGToNUdRA+dY= Received: from DLEE105.ent.ti.com (dlee105.ent.ti.com [157.170.170.35]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 393B43ul003074 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 3 Oct 2023 06:04:03 -0500 Received: from DLEE115.ent.ti.com (157.170.170.26) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Tue, 3 Oct 2023 06:04:02 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE115.ent.ti.com (157.170.170.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Tue, 3 Oct 2023 06:04:02 -0500 Received: from uda0132425.dhcp.ti.com (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 393B1Dvq129223; Tue, 3 Oct 2023 06:03:58 -0500 From: Vignesh Raghavendra To: , , , , , Wadim Egorov CC: Vignesh Raghavendra , , , , Subject: Re: [PATCH] arm64: dts: ti: phycore-am64: Add RTC interrupt pin Date: Tue, 3 Oct 2023 16:30:53 +0530 Message-ID: <169633065054.2221719.7869317058245309197.b4-ty@ti.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20230914093027.3901602-1-w.egorov@phytec.de> References: <20230914093027.3901602-1-w.egorov@phytec.de> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lipwig.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (lipwig.vger.email [0.0.0.0]); Tue, 03 Oct 2023 04:04:41 -0700 (PDT) Hi Wadim Egorov, On Thu, 14 Sep 2023 11:30:27 +0200, Wadim Egorov wrote: > Wth commit 16b26f602758 ("rtc: rv3028: Use IRQ flags obtained from device > tree if available") we can now use the interrupt pin of the RTC. > Let's add interrupt pin definitions to the SoM RTC. > > I have applied the following to branch ti-k3-dts-next on [1]. Thank you! [1/1] arm64: dts: ti: phycore-am64: Add RTC interrupt pin commit: a1cd710f56c145bc7e7fc2bfbe332d944d5338cd All being well this means that it will be integrated into the linux-next tree (usually sometime in the next 24 hours) and sent up the chain during the next merge window (or sooner if it is a relevant bug fix), however if problems are discovered then the patch may be dropped or reverted. You may get further e-mails resulting from automated or manual testing and review of the tree, please engage with people reporting problems and send followup patches addressing any issues that are reported if needed. If any updates are required or you are submitting further changes they should be sent as incremental updates against current git, existing patches will not be replaced. Please add any relevant lists and maintainers to the CCs when replying to this mail. [1] https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux.git -- Vignesh