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Date:   Tue, 3 Oct 2023 13:56:01 +0200
From:   Miquel Raynal <miquel.raynal@bootlin.com>
To:     Domenico Punzo <dpunzo@micron.com>
Cc:     Martin =?UTF-8?B?SHVuZGViw7hsbA==?= <martin@geanix.com>,
        Rouven Czerwinski <r.czerwinski@pengutronix.de>,
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        Alexander Shiyan <eagle.alexander923@gmail.com>,
        Richard Weinberger <richard@nod.at>,
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        JaimeLiao <jaimeliao.tw@gmail.com>,
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        Sean =?UTF-8?B?Tnlla2rDpnI=?= <sean@geanix.com>,
        Bean Huo <beanhuo@micron.com>
Subject: Re: [EXT] Re: [PATCH v2] mtd: rawnand: Ensure the nand chip
 supports cached reads
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Hi Domenico,

dpunzo@micron.com wrote on Tue, 3 Oct 2023 11:29:33 +0000:

> Micron Confidential
>=20
> Hello Miquel,
>=20
> Here is a short list of devices having cache read with ECC enabled.
>=20
> MT29F2G08ABAGAH4, MT29F2G08ABBGAH4, MT29F2G16ABBGAH4
> MT29F1G08ABAFAH4, MT29F1G08ABBFAH4, MT29F1G16ABBFAH4

Great! Thanks a lot.

It appears that even without internal ECC enabled we get failures on
Micron parts, so I believe there is something else that we need to
investigate. But thanks for the list, I will propose a patch preventing
the use of on-die ECC together with sequential cache reads on all parts
but the ones in this list (can be extended later).

Thanks,
Miqu=C3=A8l