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Tue, 03 Oct 2023 04:59:10 -0700 (PDT) Date: Tue, 3 Oct 2023 14:59:08 +0300 From: Serge Semin To: =?utf-8?B?S8O2cnk=?= Maincent Cc: Cai Huoqing , Manivannan Sadhasivam , Vinod Koul , Gustavo Pimentel , dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org, Thomas Petazzoni , Herve Codina Subject: Re: [PATCH v2 5/5] dmaengine: dw-edma: eDMA: Add sync read before starting the DMA transfer in remote setup Message-ID: References: <20231002131749.2977952-1-kory.maincent@bootlin.com> <20231002131749.2977952-6-kory.maincent@bootlin.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20231002131749.2977952-6-kory.maincent@bootlin.com> X-Spam-Status: No, score=-0.6 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lipwig.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (lipwig.vger.email [0.0.0.0]); Tue, 03 Oct 2023 04:59:25 -0700 (PDT) On Mon, Oct 02, 2023 at 03:17:49PM +0200, K?ry Maincent wrote: > From: Kory Maincent > > The Linked list element and pointer are not stored in the same memory as > the eDMA controller register. If the doorbell register is toggled before > the full write of the linked list a race condition error can appears. > In remote setup we can only use a readl to the memory to assured the full > write has occurred. > > Fixes: 7e4b8a4fbe2c ("dmaengine: Add Synopsys eDMA IP version 0 support") > Signed-off-by: Kory Maincent > --- > drivers/dma/dw-edma/dw-edma-v0-core.c | 22 ++++++++++++++++++++++ > 1 file changed, 22 insertions(+) > > diff --git a/drivers/dma/dw-edma/dw-edma-v0-core.c b/drivers/dma/dw-edma/dw-edma-v0-core.c > index b38786f0ad79..75c0b1fa9c40 100644 > --- a/drivers/dma/dw-edma/dw-edma-v0-core.c > +++ b/drivers/dma/dw-edma/dw-edma-v0-core.c > @@ -346,6 +346,25 @@ static void dw_edma_v0_core_write_chunk(struct dw_edma_chunk *chunk) > dw_edma_v0_write_ll_link(chunk, i, control, chunk->ll_region.paddr); > } > > +/** > + * dw_edma_v0_sync_ll_data() - sync the ll data write > + * @chunk: dma chunk > + * > + * In case of remote eDMA engine setup, the DW PCIe RP/EP internals > + * configuration registers and Application memory are normally accesse > + * over different buses. We need to insure ll data has been written before > + * toggling the doorbell register. > + */ > +static void dw_edma_v0_sync_ll_data(struct dw_edma_chunk *chunk) > +{ > + if (!(chunk->chan->dw->chip->flags & DW_EDMA_CHIP_LOCAL)) > + /* Linux memory barriers don't cater for what's required here. > + * What's required is what's here - a read of the linked > + * list region. > + */ The same comments as for [PATCH v2 4/5]. -Serge(y) > + readl(chunk->ll_region.vaddr.io); > +} > + > static void dw_edma_v0_core_start(struct dw_edma_chunk *chunk, bool first) > { > struct dw_edma_chan *chan = chunk->chan; > @@ -412,6 +431,9 @@ static void dw_edma_v0_core_start(struct dw_edma_chunk *chunk, bool first) > SET_CH_32(dw, chan->dir, chan->id, llp.msb, > upper_32_bits(chunk->ll_region.paddr)); > } > + > + dw_edma_v0_sync_ll_data(chunk); > + > /* Doorbell */ > SET_RW_32(dw, chan->dir, doorbell, > FIELD_PREP(EDMA_V0_DOORBELL_CH_MASK, chan->id)); > -- > 2.25.1 >