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[209.85.128.174]) by smtp.gmail.com with ESMTPSA id v93-20020a25abe6000000b00d81425266c1sm373700ybi.42.2023.10.03.05.34.26 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 03 Oct 2023 05:34:26 -0700 (PDT) Received: by mail-yw1-f174.google.com with SMTP id 00721157ae682-59f6e6b206fso10486567b3.3; Tue, 03 Oct 2023 05:34:26 -0700 (PDT) X-Received: by 2002:a25:c791:0:b0:d81:6e88:7cb3 with SMTP id w139-20020a25c791000000b00d816e887cb3mr13683713ybe.47.1696336465884; Tue, 03 Oct 2023 05:34:25 -0700 (PDT) MIME-Version: 1.0 References: <20230929000704.53217-1-prabhakar.mahadev-lad.rj@bp.renesas.com> <20230929000704.53217-6-prabhakar.mahadev-lad.rj@bp.renesas.com> In-Reply-To: <20230929000704.53217-6-prabhakar.mahadev-lad.rj@bp.renesas.com> From: Geert Uytterhoeven Date: Tue, 3 Oct 2023 14:34:13 +0200 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH 5/5] riscv: configs: defconfig: Enable configs required for RZ/Five SoC To: Prabhakar Cc: Magnus Damm , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Rob Herring , Krzysztof Kozlowski , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Biju Das , Lad Prabhakar Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8BIT X-Spam-Status: No, score=-0.8 required=5.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on pete.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (pete.vger.email [0.0.0.0]); Tue, 03 Oct 2023 05:34:37 -0700 (PDT) Hi Prabhakar, On Fri, Sep 29, 2023 at 2:07 AM Prabhakar wrote: > From: Lad Prabhakar > > Enable the configs required by the below IP blocks which are > present on RZ/Five SoC: > * ADC > * CANFD > * DMAC > * eMMC/SDHI > * OSTM > * RAVB (+ Micrel PHY) > * RIIC > * RSPI > * SSI (Sound+WM8978 codec) > * Thermal > * USB (PHY/RESET/OTG) > > Along with the above some core configs are enabled too, > -> CPU frequency scaling as RZ/Five does support this. > -> MTD is enabled as RSPI can be connected to flash chips > -> Enabled I2C chardev so that it enables userspace to read/write > i2c devices (similar to arm64) > -> Thermal configs as RZ/Five SoC does have thermal unit > -> GPIO regulator as we might have IP blocks for which voltage > levels are controlled by GPIOs > -> OTG configs as RZ/Five USB can support host/function > -> Gadget configs so that we can test USB function (as done in arm64 > all the gadget configs are enabled) > > Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven As I expect this to go in through the RISC-V tree, I will let the RISC-V people handle any discussion about more options that should be made modular instead of builtin. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds