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From:   Adam Ford <aford173@gmail.com>
Date:   Tue, 3 Oct 2023 08:01:49 -0500
Message-ID: <CAHCN7x+TCxbaE7Y41Yn5SpG0G5V57hwXQ7HX_ExLF1EXKtZs4w@mail.gmail.com>
Subject: Re: [PATCH 02/13] arm64: dts: imx8mp: re-parent IMX8MP_CLK_MEDIA_MIPI_PHY1_REF
To:     Benjamin Bara <bbara93@gmail.com>
Cc:     Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Conor Dooley <conor+dt@kernel.org>,
        Shawn Guo <shawnguo@kernel.org>,
        Sascha Hauer <s.hauer@pengutronix.de>,
        Pengutronix Kernel Team <kernel@pengutronix.de>,
        Fabio Estevam <festevam@gmail.com>,
        NXP Linux Team <linux-imx@nxp.com>,
        Michael Turquette <mturquette@baylibre.com>,
        Stephen Boyd <sboyd@kernel.org>,
        Russell King <linux@armlinux.org.uk>,
        Abel Vesa <abelvesa@kernel.org>, Peng Fan <peng.fan@nxp.com>,
        Frank Oltmanns <frank@oltmanns.dev>,
        Maxime Ripard <mripard@kernel.org>, devicetree@vger.kernel.org,
        linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org,
        linux-clk@vger.kernel.org,
        Benjamin Bara <benjamin.bara@skidata.com>
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On Sun, Sep 17, 2023 at 5:40=E2=80=AFPM Benjamin Bara <bbara93@gmail.com> w=
rote:
>
> From: Benjamin Bara <benjamin.bara@skidata.com>
>
> Similar to commit 07bb2e368820 ("arm64: dts: imx8mp: Fix video clock
> parents") the parent of IMX8MP_CLK_MEDIA_MIPI_PHY1_REF should be set in
> the media_blk_ctrl. Currently, if mipi_dsi is not in use, its parent is
> set to IMX8MP_VIDEO_PLL1_OUT, and might therefore clash with the
> constraints coming from a panel.

From what I can see, it looks like the IMX8MP_CLK_MEDIA_MIPI_PHY1_REF
parent is being set to IMX8MP_CLK_24M.  Isn't that the default? I also
don't think we need to set a 24MHz clock to 24MHz if that's the
default.

If that is the case, I would suggest we try to remove the assignment
altogether to make the device tree simpler and less to untangle if a
board needs to manually manipulate the clocks for some specific
reason.

adam

>
> Cc: Adam Ford <aford173@gmail.com>
> Signed-off-by: Benjamin Bara <benjamin.bara@skidata.com>
> ---
>  arch/arm64/boot/dts/freescale/imx8mp.dtsi | 14 ++++++--------
>  1 file changed, 6 insertions(+), 8 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/=
dts/freescale/imx8mp.dtsi
> index c946749a3d73..9539d747e28e 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> @@ -1640,11 +1640,6 @@ mipi_dsi: dsi@32e60000 {
>                                 clocks =3D <&clk IMX8MP_CLK_MEDIA_APB_ROO=
T>,
>                                          <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1=
_REF>;
>                                 clock-names =3D "bus_clk", "sclk_mipi";
> -                               assigned-clocks =3D <&clk IMX8MP_CLK_MEDI=
A_APB>,
> -                                                 <&clk IMX8MP_CLK_MEDIA_=
MIPI_PHY1_REF>;
> -                               assigned-clock-parents =3D <&clk IMX8MP_S=
YS_PLL1_800M>,
> -                                                        <&clk IMX8MP_CLK=
_24M>;
> -                               assigned-clock-rates =3D <200000000>, <24=
000000>;
>                                 samsung,pll-clock-frequency =3D <24000000=
>;
>                                 interrupts =3D <GIC_SPI 18 IRQ_TYPE_LEVEL=
_HIGH>;
>                                 power-domains =3D <&media_blk_ctrl IMX8MP=
_MEDIABLK_PD_MIPI_DSI_1>;
> @@ -1747,13 +1742,16 @@ media_blk_ctrl: blk-ctrl@32ec0000 {
>                                                   <&clk IMX8MP_CLK_MEDIA_=
APB>,
>                                                   <&clk IMX8MP_CLK_MEDIA_=
DISP1_PIX>,
>                                                   <&clk IMX8MP_CLK_MEDIA_=
DISP2_PIX>,
> -                                                 <&clk IMX8MP_VIDEO_PLL1=
>;
> +                                                 <&clk IMX8MP_VIDEO_PLL1=
>,
> +                                                 <&clk IMX8MP_CLK_MEDIA_=
MIPI_PHY1_REF>;
>                                 assigned-clock-parents =3D <&clk IMX8MP_S=
YS_PLL2_1000M>,
>                                                          <&clk IMX8MP_SYS=
_PLL1_800M>,
>                                                          <&clk IMX8MP_VID=
EO_PLL1_OUT>,
> -                                                        <&clk IMX8MP_VID=
EO_PLL1_OUT>;
> +                                                        <&clk IMX8MP_VID=
EO_PLL1_OUT>,
> +                                                        <&clk IMX8MP_CLK=
_24M>;
>                                 assigned-clock-rates =3D <500000000>, <20=
0000000>,
> -                                                      <0>, <0>, <1039500=
000>;
> +                                                      <0>, <0>, <1039500=
000>,
> +                                                      <24000000>;
>                                 #power-domain-cells =3D <1>;
>
>                                 lvds_bridge: bridge@5c {
>
> --
> 2.34.1
>