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Message-ID: <49bb695e-cb7b-41bf-a3ac-71a8a8417c9f@quicinc.com>
Date:   Tue, 3 Oct 2023 19:58:02 +0530
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Subject: Re: [PATCH 3/8] arm64: dts: qcom: ipq5332: Add USB Super-Speed PHY
 node
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To:     Dmitry Baryshkov <dmitry.baryshkov@linaro.org>,
        <agross@kernel.org>, <andersson@kernel.org>,
        <konrad.dybcio@linaro.org>, <vkoul@kernel.org>,
        <kishon@kernel.org>, <robh+dt@kernel.org>,
        <krzysztof.kozlowski+dt@linaro.org>, <conor+dt@kernel.org>,
        <gregkh@linuxfoundation.org>, <catalin.marinas@arm.com>,
        <will@kernel.org>, <p.zabel@pengutronix.de>,
        <geert+renesas@glider.be>, <arnd@arndb.de>,
        <neil.armstrong@linaro.org>, <nfraprado@collabora.com>,
        <u-kumar1@ti.com>, <peng.fan@nxp.com>, <quic_wcheng@quicinc.com>,
        <quic_varada@quicinc.com>, <linux-arm-msm@vger.kernel.org>,
        <linux-phy@lists.infradead.org>, <devicetree@vger.kernel.org>,
        <linux-kernel@vger.kernel.org>, <linux-usb@vger.kernel.org>,
        <linux-arm-kernel@lists.infradead.org>
CC:     <quic_kathirav@quicinc.com>, <quic_nsekar@quicinc.com>,
        <quic_srichara@quicinc.com>
References: <20230929084209.3033093-1-quic_ipkumar@quicinc.com>
 <20230929084209.3033093-4-quic_ipkumar@quicinc.com>
 <5bf11343-6ab4-43a8-b12d-f2b072ce388a@linaro.org>
From:   Praveenkumar I <quic_ipkumar@quicinc.com>
In-Reply-To: <5bf11343-6ab4-43a8-b12d-f2b072ce388a@linaro.org>
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On 9/30/2023 10:52 PM, Dmitry Baryshkov wrote:
> On 29/09/2023 11:42, Praveenkumar I wrote:
>> Add USB Super-Speed UNIPHY node and populate the phandle on
>> gcc node for the parent clock map.
>>
>> Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com>
>> ---
>>   arch/arm64/boot/dts/qcom/ipq5332.dtsi | 25 ++++++++++++++++++++++++-
>>   1 file changed, 24 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi 
>> b/arch/arm64/boot/dts/qcom/ipq5332.dtsi
>> index d3fef2f80a81..b08ffd8c094e 100644
>> --- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi
>> @@ -158,6 +158,29 @@ usbphy0: phy@7b000 {
>>               status = "disabled";
>>           };
>>   +        usbphy1: phy@4b0000 {
>
> Are there other USB PHYs on this platform?
No. Only two USB PHYs.
>
>> +            compatible = "qcom,ipq5332-usb-uniphy";
>> +            reg = <0x4b0000 0x800>;
>> +
>> +            clocks = <&gcc GCC_PCIE3X1_PHY_AHB_CLK>,
>> +                 <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
>> +                 <&gcc GCC_USB0_PIPE_CLK>;
>> +            clock-names = "ahb",
>> +                      "cfg_ahb",
>> +                      "pipe";
>> +
>> +            resets =  <&gcc GCC_USB0_PHY_BCR>;
>> +
>> +            #clock-cells = <0>;
>> +            clock-output-names = "usb0_pipe_clk_src";
>
> I'm not sure, what is the best approach her. For QMP USB and PCIe PHYs 
> we had to use fixed names historically. On the other hand for QMP DP 
> clocks we are fine with the generated names. I'd prefer the latter case.
Sure, will use the generated names.
>
>> +
>> +            qcom,phy-usb-mux-sel = <&tcsr 0x10540>;
>> +
>> +            #phy-cells = <0>;
>> +
>> +            status = "disabled";
>> +        };
>> +
>>           qfprom: efuse@a4000 {
>>               compatible = "qcom,ipq5332-qfprom", "qcom,qfprom";
>>               reg = <0x000a4000 0x721>;
>> @@ -200,7 +223,7 @@ gcc: clock-controller@1800000 {
>>                    <&sleep_clk>,
>>                    <0>,
>>                    <0>,
>> -                 <0>;
>> +                 <&usbphy1>;
>>           };
>>             tcsr_mutex: hwlock@1905000 {
>
--
Thanks,
Praveenkumar