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([2600:1700:2000:b002:6022:6438:e898:6c27]) by smtp.gmail.com with ESMTPSA id r25-20020a05620a03d900b007756fe0bb17sm717260qkm.19.2023.10.03.12.50.03 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 03 Oct 2023 12:50:03 -0700 (PDT) Message-ID: Date: Tue, 3 Oct 2023 14:50:02 -0500 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 -next 3/4] RISC-V: cacheflush: Initialize CBO variables on ACPI systems Content-Language: en-US To: Sunil V L , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-acpi@vger.kernel.org Cc: Anup Patel , Albert Ou , Alexandre Ghiti , "Rafael J . Wysocki" , Daniel Lezcano , Atish Kumar Patra , Andy Shevchenko , Conor Dooley , Palmer Dabbelt , Paul Walmsley , Thomas Gleixner , Andrew Jones , Ard Biesheuvel , Len Brown References: <20230927170015.295232-1-sunilvl@ventanamicro.com> <20230927170015.295232-4-sunilvl@ventanamicro.com> From: Samuel Holland In-Reply-To: <20230927170015.295232-4-sunilvl@ventanamicro.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lipwig.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (lipwig.vger.email [0.0.0.0]); Tue, 03 Oct 2023 12:50:16 -0700 (PDT) On 2023-09-27 12:00 PM, Sunil V L wrote: > Using new interface to get the CBO block size information in RHCT, > initialize the variables on ACPI platforms. > > Signed-off-by: Sunil V L > --- > arch/riscv/mm/cacheflush.c | 37 +++++++++++++++++++++++++++++++------ > 1 file changed, 31 insertions(+), 6 deletions(-) > > diff --git a/arch/riscv/mm/cacheflush.c b/arch/riscv/mm/cacheflush.c > index f1387272a551..8e59644e473c 100644 > --- a/arch/riscv/mm/cacheflush.c > +++ b/arch/riscv/mm/cacheflush.c > @@ -3,7 +3,9 @@ > * Copyright (C) 2017 SiFive > */ > > +#include > #include > +#include > #include > > #ifdef CONFIG_SMP > @@ -124,15 +126,38 @@ void __init riscv_init_cbo_blocksizes(void) > unsigned long cbom_hartid, cboz_hartid; > u32 cbom_block_size = 0, cboz_block_size = 0; > struct device_node *node; > + struct acpi_table_header *rhct; > + acpi_status status; > + unsigned int cpu; > + > + if (!acpi_disabled) { > + status = acpi_get_table(ACPI_SIG_RHCT, 0, &rhct); > + if (ACPI_FAILURE(status)) > + return; > + } > > - for_each_of_cpu_node(node) { > - /* set block-size for cbom and/or cboz extension if available */ > - cbo_get_block_size(node, "riscv,cbom-block-size", > - &cbom_block_size, &cbom_hartid); > - cbo_get_block_size(node, "riscv,cboz-block-size", > - &cboz_block_size, &cboz_hartid); > + for_each_possible_cpu(cpu) { > + if (acpi_disabled) { > + node = of_cpu_device_node_get(cpu); > + if (!node) { > + pr_warn("Unable to find cpu node\n"); > + continue; > + } > + > + /* set block-size for cbom and/or cboz extension if available */ > + cbo_get_block_size(node, "riscv,cbom-block-size", > + &cbom_block_size, &cbom_hartid); > + cbo_get_block_size(node, "riscv,cboz-block-size", > + &cboz_block_size, &cboz_hartid); This leaks a reference to the device node. > + } else { > + acpi_get_cbo_block_size(rhct, cpu, &cbom_block_size, > + &cboz_block_size, NULL); This function loops through the whole RHCT already. Why do we need to call it for each CPU? Can't we just call it once, and have it do the same consistency checks as cbo_get_block_size()? In that case, the DT path could keep the for_each_of_cpu_node() loop. Regards, Samuel > + } > } > > + if (!acpi_disabled && rhct) > + acpi_put_table((struct acpi_table_header *)rhct); > + > if (cbom_block_size) > riscv_cbom_block_size = cbom_block_size; >