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[2620:137:e000::3:5]) by mx.google.com with ESMTPS id az1-20020a056a02004100b0056fa1bc208esi2513007pgb.722.2023.10.03.15.56.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Oct 2023 15:56:02 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:5 as permitted sender) client-ip=2620:137:e000::3:5; Authentication-Results: mx.google.com; dkim=pass header.i=@bootlin.com header.s=gm1 header.b=ZwCwEho1; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:5 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=bootlin.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by groat.vger.email (Postfix) with ESMTP id D973E81228B1; Tue, 3 Oct 2023 15:55:51 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at groat.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231980AbjJCWzk (ORCPT + 99 others); Tue, 3 Oct 2023 18:55:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56998 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231504AbjJCWzj (ORCPT ); Tue, 3 Oct 2023 18:55:39 -0400 Received: from relay7-d.mail.gandi.net (relay7-d.mail.gandi.net [IPv6:2001:4b98:dc4:8::227]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1F4369E for ; Tue, 3 Oct 2023 15:55:32 -0700 (PDT) Received: by mail.gandi.net (Postfix) with ESMTPSA id 2193D20002; Tue, 3 Oct 2023 22:55:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1696373731; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=URmNuKdevm4LxKsOW1JK28nG3SSACbwi+Sok++gB3OQ=; b=ZwCwEho1chdHhVUIoizblQAitK9IQ20h6KgjR4v5EQEEDKMiojtMoIb3mMUli12+SdJpvj RpgQUjijZJa1qKD2ZS2/bT+c8XXvEtQ0LJ6ocNGCP9PArNgvGXj9Tq4xkrGCu3jAU5KHjU mpqMRddxETvsOSGGMK/SCM7+qM+Hi2CTaNM8TlkEztDDsKfEojXd8cKRJXAzjSchsyXal7 uDK8HTBVaUnVFeOjqhyEQUDWp1VksJYIwsjuoi0ERmQd18MvjhuMT5tt+rnBIHSXH4/f0b TExVD3Ac7JZZSnCC4EIB4LlDXghPeUbgH6DOmSdwvARQ6S5nS76bHu5w7uofug== Date: Wed, 4 Oct 2023 00:55:25 +0200 From: Miquel Raynal To: William Zhang Cc: dregan@mail.com, bcm-kernel-feedback-list@broadcom.com, linux-mtd@lists.infradead.org, f.fainelli@gmail.com, rafal@milecki.pl, joel.peshkin@broadcom.com, computersforpeace@gmail.com, dan.beygelman@broadcom.com, frieder.schrempf@kontron.de, linux-kernel@vger.kernel.org, vigneshr@ti.com, richard@nod.at, bbrezillon@kernel.org, kdasu.kdev@gmail.com Subject: Re: [PATCH v2] mtd: rawnand: brcmnand: Initial exec_op implementation Message-ID: <20231004005525.3f406823@xps-13> In-Reply-To: <37416f2e-f150-cc8f-76bd-3d54f9e25d08@broadcom.com> References: <20230922162424.4a7b27ec@xps-13> <20231002143527.4ccf254a@xps-13> <04350e70-6ef0-4998-664f-20b96b63b0f4@broadcom.com> <20231003112819.53707d54@xps-13> <37416f2e-f150-cc8f-76bd-3d54f9e25d08@broadcom.com> Organization: Bootlin X-Mailer: Claws Mail 4.0.0 (GTK+ 3.24.33; x86_64-pc-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-GND-Sasl: miquel.raynal@bootlin.com X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on groat.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (groat.vger.email [0.0.0.0]); Tue, 03 Oct 2023 15:55:52 -0700 (PDT) Hi William, william.zhang@broadcom.com wrote on Tue, 3 Oct 2023 11:46:25 -0700: > Hi Miquel, >=20 > On 10/03/2023 02:28 AM, Miquel Raynal wrote: > > Hi William, > >=20 > > william.zhang@broadcom.com wrote on Mon, 2 Oct 2023 12:57:01 -0700: > > =20 > >> Hi Miquel, > >> > >> On 10/02/2023 05:35 AM, Miquel Raynal wrote: =20 > >>> Hi David, > >>> > >>> dregan@mail.com wrote on Sat, 30 Sep 2023 03:57:35 +0200: =20 > >>> >>>> Initial exec_op implementation for Broadcom STB, Broadband an= d iProc SoC =20 > >>>> This adds exec_op and removes the legacy interface. > >>>> > >>>> Signed-off-by: David Regan > >>>> Reviewed-by: William Zhang > >>>> > >>>> --- =20 > >>>> >>> =20 > >>> ... =20 > >>> >>>> +static int brcmnand_parser_exec_matched_op(struct nand_chip = *chip, =20 > >>>> + const struct nand_subop *subop) > >>>> +{ > >>>> + struct brcmnand_host *host =3D nand_get_controller_data(chip); > >>>> + struct brcmnand_controller *ctrl =3D host->ctrl; > >>>> + struct mtd_info *mtd =3D nand_to_mtd(chip); > >>>> + const struct nand_op_instr *instr =3D &subop->instrs[0]; > >>>> + unsigned int i; > >>>> + int ret =3D 0; > >>>> + > >>>> + for (i =3D 0; i < subop->ninstrs; i++) { > >>>> + instr =3D &subop->instrs[i]; > >>>> + > >>>> + if ((instr->type =3D=3D NAND_OP_CMD_INSTR) && > >>>> + (instr->ctx.cmd.opcode =3D=3D NAND_CMD_STATUS)) > >>>> + ctrl->status_cmd =3D 1; > >>>> + else if (ctrl->status_cmd && (instr->type =3D=3D NAND_OP_DATA_IN_= INSTR)) { > >>>> + /* > >>>> + * need to fake the nand device write protect because nand_base = does a > >>>> + * nand_check_wp which calls nand_status_op NAND_CMD_STATUS whic= h checks > >>>> + * that the nand is not write protected before an operation star= ts. > >>>> + * The problem with this is it's done outside exec_op so the nan= d is > >>>> + * write protected and this check will fail until the write or e= rase > >>>> + * or write back operation actually happens where we turn off wp. > >>>> + */ > >>>> + u8 *in; > >>>> + > >>>> + ctrl->status_cmd =3D 0; > >>>> + > >>>> + instr =3D &subop->instrs[i]; > >>>> + in =3D instr->ctx.data.buf.in; > >>>> + in[0] =3D brcmnand_status(host) | NAND_STATUS_WP; /* hide WP sta= tus */ =20 > >>> > >>> I don't understand why you are faking the WP bit. If it's set, > >>> brcmnand_status() should return it and you should not care about it. = If > >>> it's not however, can you please give me the path used when we have > >>> this issue? Either we need to modify the core or we need to provide > >>> additional helpers in this driver to circumvent the faulty path. =20 > >> > >> The reason we have to hide wp status for status command is because > >> nand_base calls nand_check_wp at the very beginning of write and erase > >> function. This applies to both exec_op path and legacy path. With > >> Broadcom nand controller and most of our board design using the WP pin > >> and have it asserted by default, the nand_check_wp function will fail > >> and write/erase aborts. This workaround has been there before this > >> exec_op patch. > >> > >> I agree it is ugly and better to be addressed in the nand base code. A= nd > >> I understand Broadcom's WP approach may sound a bit over cautious but = we > >> want to make sure no spurious erase/write can happen under any > >> circumstance except software explicitly want to write and erase. WP is > >> standard nand chip pin and I think most the nand controller has that > >> that pin in the design too but it is possible it is not used and > >> bootloader can de-assert the pin and have a always-writable nand flash > >> for linux. So maybe we can add nand controller dts option "nand-use-wp= ". > >> If this property exist and set to 1, wp control is in use and nand > >> driver need to control the pin on/ff as needed when doing write and > >> erase function. Also nand base code should not call nand_check_wp when > >> wp is in use. Then we can remove the faking WP status workaround. > >> =20 > >>> >>>> + } else if (instr->type =3D=3D NAND_OP_WAITRDY_INSTR) { =20 > >>>> + ret =3D bcmnand_ctrl_poll_status(host, NAND_CTRL_RDY, NAND_CTRL_= RDY, 0); > >>>> + if (ctrl->wp_cmd) { > >>>> + ctrl->wp_cmd =3D 0; > >>>> + brcmnand_wp(mtd, 1); =20 > >>> > >>> This ideally should disappear. =20 > >>> >> Maybe we can have the destructive operation patch from Borris. = =20 > >> Controller driver still need to assert/deassert the pin if it uses nand > >> wp feature but at least it does not need to guess the op code. =20 > >=20 > > Ah, yeah, I get it. > >=20 > > Please be my guest, you can revive this patch series (might need light > > tweaking, nothing big) and also take inspiration from it if necessary: > > https://github.com/bbrezillon/linux/commit/e612e1f2c69a33ac5f2c91d13669= f0f172d58717 > > https://github.com/bbrezillon/linux/commit/4ec6f8d8d83f5aaca5d1877f02d4= 8da96d41fcba > > https://github.com/bbrezillon/linux/commit/11b4acffd761c4928652d7028d19= fcd6f45e4696 > > =20 > Sure we will incorporate the destructive operation patch and provide a > new revision. >=20 > The WP status workaround will stay at least for this change. If you > think my suggestion using a dts setting above is okay, we can provide a > patch for that as well. Or if you have any other idea or suggestion, > we'd like to hear too. I thought this was not needed as Boris initial conversion did not need it. The goal is to get rid of this workaround. Thanks, Miqu=C3=A8l