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From:   Pankaj Gupta <pankaj.gupta@nxp.com>
To:     Rob Herring <robh@kernel.org>
CC:     "shawnguo@kernel.org" <shawnguo@kernel.org>,
        "s.hauer@pengutronix.de" <s.hauer@pengutronix.de>,
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        "conor+dt@kernel.org" <conor+dt@kernel.org>,
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        "festevam@gmail.com" <festevam@gmail.com>,
        dl-linux-imx <linux-imx@nxp.com>,
        "davem@davemloft.net" <davem@davemloft.net>,
        "krzysztof.kozlowski+dt@linaro.org" 
        <krzysztof.kozlowski+dt@linaro.org>,
        "linux-arm-kernel@lists.infradead.org" 
        <linux-arm-kernel@lists.infradead.org>,
        "devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        Gaurav Jain <gaurav.jain@nxp.com>,
        "alexander.stein@ew.tq-group.com" <alexander.stein@ew.tq-group.com>,
        Varun Sethi <V.Sethi@nxp.com>
Subject: RE: [EXT] Re: [PATCH v6 02/11] dt-bindings: arm: fsl: add imx-se-fw
 binding doc
Thread-Topic: [EXT] Re: [PATCH v6 02/11] dt-bindings: arm: fsl: add imx-se-fw
 binding doc
Thread-Index: AQHZ8T3cp/FWHmHt10GsVHBXrCASpLAwlzyAgAdf5cA=
Date:   Wed, 4 Oct 2023 04:10:55 +0000
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References: <20230927175401.1962733-1-pankaj.gupta@nxp.com>
 <20230927175401.1962733-3-pankaj.gupta@nxp.com>
 <20230928185159.GA1035361-robh@kernel.org>
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> -----Original Message-----
> From: Rob Herring <robh@kernel.org>
> Sent: Friday, September 29, 2023 12:22 AM
> To: Pankaj Gupta <pankaj.gupta@nxp.com>
> Cc: shawnguo@kernel.org; s.hauer@pengutronix.de;
> kernel@pengutronix.de; clin@suse.com; conor+dt@kernel.org;
> pierre.gondois@arm.com; festevam@gmail.com; dl-linux-imx <linux-
> imx@nxp.com>; davem@davemloft.net; krzysztof.kozlowski+dt@linaro.org;
> linux-arm-kernel@lists.infradead.org; devicetree@vger.kernel.org; linux-
> kernel@vger.kernel.org; Gaurav Jain <gaurav.jain@nxp.com>;
> alexander.stein@ew.tq-group.com; Varun Sethi <V.Sethi@nxp.com>
> Subject: [EXT] Re: [PATCH v6 02/11] dt-bindings: arm: fsl: add imx-se-fw
> binding doc
>=20
> Caution: This is an external email. Please take care when clicking links =
or
> opening attachments. When in doubt, report the message using the 'Report
> this email' button
>=20
>=20
> On Wed, Sep 27, 2023 at 11:23:52PM +0530, Pankaj Gupta wrote:
> > The NXP's i.MX EdgeLock Enclave, a HW IP creating an embedded secure
> > enclave within the SoC boundary to enable features like
> > - HSM
> > - SHE
> > - V2X
> >
> > Communicates via message unit with linux kernel. This driver is
> > enables communication ensuring well defined message sequence protocol
> > between Application Core and enclave's firmware.
> >
> > Driver configures multiple misc-device on the MU, for multiple
> > user-space applications can communicate on single MU.
> >
> > It exists on some i.MX processors. e.g. i.MX8ULP, i.MX93 etc.
> >
> > Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
> > ---
> >  .../bindings/firmware/fsl,imx-se-fw.yaml      | 73 +++++++++++++++++++
> >  1 file changed, 73 insertions(+)
> >  create mode 100644
> > Documentation/devicetree/bindings/firmware/fsl,imx-se-fw.yaml
> >
> > diff --git
> > a/Documentation/devicetree/bindings/firmware/fsl,imx-se-fw.yaml
> > b/Documentation/devicetree/bindings/firmware/fsl,imx-se-fw.yaml
> > new file mode 100644
> > index 000000000000..d250794432b3
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/firmware/fsl,imx-se-fw.yaml
> > @@ -0,0 +1,73 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2
> > +---
> > +$id:
> >
> +https://eur01.safelinks.protection.outlook.com/?url=3Dhttp%3A%2F%2Fdevi
> > +cetree.org%2Fschemas%2Ffirmware%2Ffsl%2Cimx-se-
> fw.yaml%23&data=3D05%7C0
> >
> +1%7Cpankaj.gupta%40nxp.com%7C5ec9b97100834814d30608dbc054010a%7
> C686ea
> >
> +1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C638315239256248220%7CUnk
> nown%7C
> >
> +TWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwi
> LCJXV
> >
> +CI6Mn0%3D%7C3000%7C%7C%7C&sdata=3D5%2BuUxUzFCRHsi17vX83tGcJijp
> HsNAxd5Fu
> > +Ws4qT9Lw%3D&reserved=3D0
> > +$schema:
> >
> +https://eur01.safelinks.protection.outlook.com/?url=3Dhttp%3A%2F%2Fdevi
> > +cetree.org%2Fmeta-
> schemas%2Fcore.yaml%23&data=3D05%7C01%7Cpankaj.gupta%
> >
> +40nxp.com%7C5ec9b97100834814d30608dbc054010a%7C686ea1d3bc2b4c6f
> a92cd9
> >
> +9c5c301635%7C0%7C0%7C638315239256248220%7CUnknown%7CTWFpbGZ
> sb3d8eyJWI
> >
> +joiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7
> C3000%
> >
> +7C%7C%7C&sdata=3Do1LjAT7gJVTb66L21HyhfY9dGh8uKIFNHWKg%2FLNBMO
> 8%3D&reser
> > +ved=3D0
> > +
> > +title: NXP i.MX EdgeLock Enclave Firmware (ELEFW)
> > +
> > +maintainers:
> > +  - Pankaj Gupta <pankaj.gupta@nxp.com>
> > +
> > +description:
>=20
> Need '|' to preserve formatting.

Accepted.
>=20
> > +  The NXP's i.MX EdgeLock Enclave, a HW IP creating an embedded
> > + secure enclave within the SoC boundary to enable features like
> > +  - HSM
> > +  - SHE
> > +  - V2X
> > +
> > +  It uses message unit to communicate and coordinate to pass messages
> > + (e.g., data,  status and control) through its interfaces.
> > +
> > +properties:
> > +  compatible:
> > +    enum:
> > +      - fsl,imx8ulp-se-fw
> > +      - fsl,imx93-se-fw
>=20
> The firmware is not compatible across chips?
=09
The secure-enclave hardware varies from one SoC to another.
Hence, FW varies too, from one SoC, to other.

>=20
> > +
> > +  mboxes:
> > +    description:
> > +      All MU channels must be within the same MU instance. Cross insta=
nces
> are
> > +      not allowed. Users need to ensure that used MU instance does not
> conflict
> > +      with other execution environments.
> > +    items:
> > +      - description: TX0 MU channel
> > +      - description: RX0 MU channel
> > +
> > +  mbox-names:
> > +    items:
> > +      - const: tx
> > +      - const: rx
> > +
> > +  fsl,mu-id:
> > +    $ref: /schemas/types.yaml#/definitions/uint32
> > +    description:
> > +      Identifier to the message-unit among the multiple message-unit t=
hat
> exists on SoC.
> > +      Per message-unit, multiple misc-devices are created, that are
> > + used by userspace
>=20
> Extra space in there.

Accepted.
>=20
> Wrap lines at 80 unless there's a benefit to going to 100.
>=20
Accepted.

> > +      application as logical-waiter and logical-receiver.
> > +
> > +  memory-region:
> > +    items:
> > +      - description: Reserved memory region that can be accessed by
> firmware. Used for
> > +          exchanging the buffers between driver and firmware.
> > +
> > +  fsl,sram:
>=20
> Just the common 'sram' property.
Ok

>=20
> > +    description: Phandle to the device SRAM
>=20
> Used for what?
Accepted and will add the details on the usage.

>=20
> > +    $ref: /schemas/types.yaml#/definitions/phandle-array
> > +
> > +required:
> > +  - compatible
> > +  - mboxes
> > +  - mbox-names
> > +  - fsl,mu-id
>=20
> How is memory-region optional?
Depending on the type of enclave IP and the FW, memory-region is configured=
 optionally.
For i.MX8ULP and i.MX93, it is required. For i.MX8DXL, it is not required.
>=20
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > +  - |
> > +    ele_fw: se-fw {
>=20
> Drop unused labels.
I am sorry, if I am not able to understand your point here.
But, all the below labels are getting used.
I can remove the fsl,mu-id. Will do it in V7.

>=20
> > +      compatible =3D "fsl,imx8ulp-se-fw";
> > +      mbox-names =3D "tx", "rx";
> > +      mboxes =3D <&s4muap 0 0>, <&s4muap 1 0>;
> > +      fsl,mu-id =3D <2>;
> > +    };
> > --
> > 2.34.1
> >