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Date:   Wed, 4 Oct 2023 09:44:55 +0200
From:   Miquel Raynal <miquel.raynal@bootlin.com>
To:     niravkumar.l.rabara@intel.com
Cc:     Richard Weinberger <richard@nod.at>,
        Vignesh Raghavendra <vigneshr@ti.com>,
        Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Conor Dooley <conor+dt@kernel.org>,
        linux-mtd@lists.infradead.org, devicetree@vger.kernel.org,
        linux-kernel@vger.kernel.org
Subject: Re: [PATCH] dt-bindings: mtd: cadence: convert
 cadence-nand-controller.txt to yaml
Message-ID: <20231004094455.1a6a19e1@xps-13>
In-Reply-To: <20231004061214.17176-1-niravkumar.l.rabara@intel.com>
References: <20231004061214.17176-1-niravkumar.l.rabara@intel.com>
Organization: Bootlin
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Hello,

niravkumar.l.rabara@intel.com wrote on Wed,  4 Oct 2023 14:12:14 +0800:

> From: Niravkumar L Rabara <niravkumar.l.rabara@intel.com>
>=20
> Convert cadence-nand-controller.txt to yaml format.

Looks good to me, one question below.

> Signed-off-by: Niravkumar L Rabara <niravkumar.l.rabara@intel.com>
> ---
>  .../devicetree/bindings/mtd/cadence,nand.yaml | 73 +++++++++++++++++++
>  .../bindings/mtd/cadence-nand-controller.txt  | 53 --------------
>  2 files changed, 73 insertions(+), 53 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/mtd/cadence,nand.ya=
ml
>  delete mode 100644 Documentation/devicetree/bindings/mtd/cadence-nand-co=
ntroller.txt
>=20
> diff --git a/Documentation/devicetree/bindings/mtd/cadence,nand.yaml b/Do=
cumentation/devicetree/bindings/mtd/cadence,nand.yaml
> new file mode 100644
> index 000000000000..781812ac702f
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mtd/cadence,nand.yaml
> @@ -0,0 +1,73 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/mtd/cadence,nand.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Cadence NAND controller
> +
> +maintainers:
> +  - Niravkumar L Rabara <niravkumar.l.rabara@intel.com>
> +
> +allOf:
> +  - $ref: nand-controller.yaml
> +
> +properties:
> +  compatible:
> +    items:
> +      - const: cdns,hp-nfc
> +
> +  reg:
> +    items:
> +      - description: Address and length of the controller register set
> +      - description: Address and length of the Slave DMA data port
> +
> +  reg-names:
> +    items:
> +      - const: reg
> +      - const: sdma
> +
> +  interrupts:
> +    maxItems: 1
> +
> +  clocks:
> +    maxItems: 1
> +
> +  dmas:
> +    maxItems: 1
> +
> +  cdns,board-delay-ps:
> +    description: |
> +      Estimated Board delay. The value includes the total round trip
> +      delay for the signals and is used for deciding on values associated
> +      with data read capture. The example formula for SDR mode is the
> +      following.
> +      board delay =3D RE#PAD delay + PCB trace to device + PCB trace fro=
m device
> +      + DQ PAD delay
> +
> +required:
> +  - compatible
> +  - reg
> +  - reg-names
> +  - interrupts
> +  - clocks
> +
> +unevaluatedProperties: false
> +
> +examples:
> +  - |
> +      nand-controller@10b80000 {
> +        compatible =3D "cdns,hp-nfc";
> +        reg =3D <0x10b80000 0x10000>,
> +            <0x10840000 0x10000>;
> +        reg-names =3D "reg", "sdma";
> +        #address-cells =3D <1>;
> +        #size-cells =3D <0>;
> +        interrupts =3D <0 97 4>;
> +        clocks =3D <&nf_clk>;
> +        cdns,board-delay-ps =3D <4830>;
> +
> +        nand@0 {
> +            reg =3D <0>;
> +        };
> +      };
> diff --git a/Documentation/devicetree/bindings/mtd/cadence-nand-controlle=
r.txt b/Documentation/devicetree/bindings/mtd/cadence-nand-controller.txt
> deleted file mode 100644
> index d2eada5044b2..000000000000
> --- a/Documentation/devicetree/bindings/mtd/cadence-nand-controller.txt
> +++ /dev/null
> @@ -1,53 +0,0 @@
> -* Cadence NAND controller
> -
> -Required properties:
> -  - compatible : "cdns,hp-nfc"
> -  - reg : Contains two entries, each of which is a tuple consisting of a
> -	  physical address and length. The first entry is the address and
> -	  length of the controller register set. The second entry is the
> -	  address and length of the Slave DMA data port.
> -  - reg-names: should contain "reg" and "sdma"
> -  - #address-cells: should be 1. The cell encodes the chip select connec=
tion.
> -  - #size-cells : should be 0.
> -  - interrupts : The interrupt number.
> -  - clocks: phandle of the controller core clock (nf_clk).
> -
> -Optional properties:
> -  - dmas: shall reference DMA channel associated to the NAND controller
> -  - cdns,board-delay-ps : Estimated Board delay. The value includes the =
total
> -    round trip delay for the signals and is used for deciding on values
> -    associated with data read capture. The example formula for SDR mode =
is
> -    the following:
> -    board delay =3D RE#PAD delay + PCB trace to device + PCB trace from =
device
> -    + DQ PAD delay
> -
> -Child nodes represent the available NAND chips.

This is not fully pictured in the current schema, by referencing
nand-controller.yaml I believe you allow all kind of direct
partitioning (which is legacy, and not supposed to be supported here).
Can you try to define a partition directly within the controller node
in the example and see whether it still passes the checks?

Thanks,
Miqu=C3=A8l