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Date:   Wed, 4 Oct 2023 19:43:29 +0800
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Subject: Re: [PATCH 4/5] riscv: dts: sophgo: add initial CV1800B SoC device
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To:     Conor Dooley <conor@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Cc:     Jisheng Zhang <jszhang@kernel.org>,
        Thomas Gleixner <tglx@linutronix.de>,
        Marc Zyngier <maz@kernel.org>,
        Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Conor Dooley <conor+dt@kernel.org>,
        Palmer Dabbelt <palmer@dabbelt.com>,
        Paul Walmsley <paul.walmsley@sifive.com>,
        Albert Ou <aou@eecs.berkeley.edu>,
        Daniel Lezcano <daniel.lezcano@linaro.org>,
        Anup Patel <anup@brainfault.org>, linux-kernel@vger.kernel.org,
        devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
        Inochi Amaoto <inochiama@outlook.com>, chao.wei@sophgo.com,
        xiaoguang.xing@sophgo.com
References: <20230930123937.1551-1-jszhang@kernel.org>
 <20230930123937.1551-5-jszhang@kernel.org>
 <MA0P287MB033277186E21A09127407452FECBA@MA0P287MB0332.INDP287.PROD.OUTLOOK.COM>
 <37021ef8-55e2-4116-8201-2ab7df9e0fc1@linaro.org>
 <20231004-caregiver-deserve-71849c94dcfb@spud>
From:   Chen Wang <unicorn_wang@outlook.com>
In-Reply-To: <20231004-caregiver-deserve-71849c94dcfb@spud>
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在 2023/10/4 17:13, Conor Dooley 写道:
> On Wed, Oct 04, 2023 at 09:57:33AM +0200, Krzysztof Kozlowski wrote:
>> On 04/10/2023 09:23, Chen Wang wrote:
>>> 在 2023/9/30 20:39, Jisheng Zhang 写道:
>>>> Add initial device tree for the CV1800B RISC-V SoC by SOPHGO.
>>>>
>>>> Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
>>>> ---
>>>>    arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 117 ++++++++++++++++++++++++
>>>>    1 file changed, 117 insertions(+)
>>>>    create mode 100644 arch/riscv/boot/dts/sophgo/cv1800b.dtsi
>>> Hi, Jisheng, as far as I know, sg2042 and cv180x are now tracked by
>>> different people and even in sophgo, they are two independent
>>> projects(sg2042 is target for HPC and cv180x is target for embeded
>>> device). To facilitate future management and review, I recommend
>>> registering the maintainer information in two entries in MAINTAINERS.
>>> The example is as follows:
>>>
>>> ```
>>>
>>> SOPHGO CV180X DEVICETREES
>>> M:  Jisheng Zhang <jszhang@kernel.org>
>>> F:  arch/riscv/boot/dts/sophgo/cv1800b-milkv-duo.dts
>>> F:  arch/riscv/boot/dts/sophgo/cv1800b.dtsi
>>>
>>> SOPHGO SG2042 DEVICETREES
>>> M:  Chao Wei <chao.wei@sophgo.com>
>>> M:  Chen Wang <unicornxw@gmail.com>
>>> S:  Maintained
>>> F:  arch/riscv/boot/dts/sophgo/Makefile
>>> F:  arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
>>> F:  arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts
>>> F:  arch/riscv/boot/dts/sophgo/sg2042.dtsi
>>> F:  Documentation/devicetree/bindings/riscv/sophgo.yaml
>>> ```
>>>
>>> For Makefile and sophgo.yaml such common files, just keep in sg2042
>>> entry should be fine.
>>>
>>> @Conor, what do you think?
>> We do no have usually per-board maintainer entries (with few
>> exceptions). I strongly prefer this one instead:
>>
>> https://lore.kernel.org/all/829b122da52482707b783dc3d93d3ff0179cb0ca.camel@perches.com/
> I don't like the suggestion here for a different reason! While I'm fine
> with having some per-board SoC maintainers, esp. since the cv1800 stuff
> is very different to the sg2042, I want to see someone step up to apply
> the patches for the whole arch/riscv/boot/dts/sophgo/ directory once more
> comfortable with the process, not reduce the entry to cover just the 64
> core SoC.
>
> Thanks,
> Conor.
Thanks, Conor and Krzystof.  Agree with you, it would be better to keep 
only one entry for arch/riscv/boot/dts/sophgo/ directory. I will discuss 
with other people working on sophgo and specify a unified maintenance 
task to maintain files under it.