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From:   "Mehta, Piyush" <piyush.mehta@amd.com>
To:     Rob Herring <robh@kernel.org>
CC:     "gregkh@linuxfoundation.org" <gregkh@linuxfoundation.org>,
        "Simek, Michal" <michal.simek@amd.com>,
        "krzysztof.kozlowski+dt@linaro.org" 
        <krzysztof.kozlowski+dt@linaro.org>,
        "conor+dt@kernel.org" <conor+dt@kernel.org>,
        "peter.chen@kernel.org" <peter.chen@kernel.org>,
        "linus.walleij@linaro.org" <linus.walleij@linaro.org>,
        "paul@crapouillou.net" <paul@crapouillou.net>,
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        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        "git (AMD-Xilinx)" <git@amd.com>
Subject: RE: [RFC PATCH 1/3] dt-binding: usb: ulpi-phy: add ulpi-phy binding
Thread-Topic: [RFC PATCH 1/3] dt-binding: usb: ulpi-phy: add ulpi-phy binding
Thread-Index: AQHZ8qEa5JeYHGbt0EyV+BYDViGoorA2vp2AgAC7O0A=
Date:   Wed, 4 Oct 2023 11:45:24 +0000
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Hi All,

> -----Original Message-----
> From: Rob Herring <robh@kernel.org>
> Sent: Monday, October 2, 2023 10:30 PM
> To: Mehta, Piyush <piyush.mehta@amd.com>
> Cc: gregkh@linuxfoundation.org; Simek, Michal <michal.simek@amd.com>;
> krzysztof.kozlowski+dt@linaro.org; conor+dt@kernel.org;
> peter.chen@kernel.org; linus.walleij@linaro.org; paul@crapouillou.net;
> arnd@arndb.de; linux-usb@vger.kernel.org; devicetree@vger.kernel.org; lin=
ux-
> kernel@vger.kernel.org; git (AMD-Xilinx) <git@amd.com>
> Subject: Re: [RFC PATCH 1/3] dt-binding: usb: ulpi-phy: add ulpi-phy bind=
ing
>=20
> On Fri, Sep 29, 2023 at 12:18:50PM +0530, Piyush Mehta wrote:
> > Create an ulpi-phy binding to read and write PHY registers with
> > explicit control of the address and data using the usb.VIEWPORT registe=
r.
> >
> > Signed-off-by: Piyush Mehta <piyush.mehta@amd.com>
> > ---
> > This binding patch was created to support generic platforms. This
> > binding will be modified in accordance with patch [3/3] procedures.
> > One of the approch may be Create a zynq phy platform driver in
> > "driver/usb/phy" with driver source "phy-ulpi-zynq-usb.c" and then the
> > binding will be particular to the Xilinx/AMD zynq platform.
> >
> > This binding was built with the Zynq hardware design example in
> > consideration of as a generic platform. The viewport provide access
> > the Chipidea controller to interface with the ULPI PHY.
> > ---
> >  .../devicetree/bindings/usb/ulpi-phy.yaml     | 48 +++++++++++++++++++
> >  1 file changed, 48 insertions(+)
> >  create mode 100644
> > Documentation/devicetree/bindings/usb/ulpi-phy.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/usb/ulpi-phy.yaml
> > b/Documentation/devicetree/bindings/usb/ulpi-phy.yaml
> > new file mode 100644
> > index 000000000000..490b2f610129
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/usb/ulpi-phy.yaml
> > @@ -0,0 +1,48 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/usb/ulpi-phy.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: ULPI PHY- Generic platform
> > +
> > +maintainers:
> > +  - Piyush Mehta <piyush.mehta@amd.com>
> > +
> > +properties:
> > +  compatible:
> > +    const: ulpi-phy
> > +
> > +  reg:
> > +    maxItems: 1
> > +
> > +  '#phy-cells':
> > +    const: 0
> > +
> > +  external-drv-vbus:
> > +    description:
> > +      If present, configure ulpi-phy external supply to drive 5V on VB=
us.
> > +    type: boolean
> > +
> > +  view-port:
> > +    $ref: /schemas/types.yaml#/definitions/uint32
> > +    description:
> > +      Address to read and write PHY registers with explicit control of
> > +      the address and data using the usb.VIEWPORT register.
> > +
> > +required:
> > +  - compatible
> > +  - reg
> > +  - view-port
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > +  - |
> > +    phy0@e0002000 {
> > +        compatible =3D "ulpi-phy";
> > +        #phy-cells =3D <0x00>;
> > +        reg =3D <0xe0002000 0x1000>;
> > +        view-port =3D <0x170>;
>=20
> I don't understand. Do you have an MMIO address and the VIEWPORT address
> to the PHY? You need both?

Yes, we need both.=20

The ULPI Link wrapper passes-through packet data and interprets Rx commands=
 as well as send Tx
commands and provide viewport services to the software. The ULPI link wrapp=
er interfaces between
the port controller (a bus similar to UTMI+ that connects to the rest of th=
e controller and its registers)
and the ULPI interface.

Name XUSBPS_ULPIVIEW_OFFSET
Address 0x00000170

Description ULPI Viewport

The register provides indirect access to the ULPI PHY register set. Althoug=
h the core performs access
to the ULPI PHY register set, there may be extraordinary circumstances wher=
e software may need direct
access.

ULPI PHY Viewport
The ULPI viewport provides a mechanism for software to read and write PHY r=
egisters with explicit
control of the address and data using the usb.VIEWPORT register. An interru=
pt is generated when a
transaction is complete, including when the requested read data is availabl=
e.

>=20
> There's already a defined binding for ULPI bus:
>=20
> Documentation/devicetree/bindings/usb/ulpi.txt
>=20
> Why can't you use/expand that?
>=20
> Rob

We need your input to determine the best approach . We did preliminary rese=
arch and discovered few possibilities:

USB Node {
	.............
	ULPI PHY Node {  // child node
		.................
		compatible =3D "ulpi-phy-";
		#phy-cells =3D <0x00>;
		..............	=09
	};
};

https://github.com/torvalds/linux/blob/master/Documentation/devicetree/bind=
ings/phy/qcom%2Cusb-hs-phy.yaml#L100
https://github.com/torvalds/linux/blob/master/Documentation/devicetree/bind=
ings/usb/ci-hdrc-usb2.yaml#L338
https://github.com/torvalds/linux/blob/master/drivers/usb/chipidea/ci_hdrc_=
msm.c#L245
https://github.com/torvalds/linux/blob/master/drivers/phy/qualcomm/phy-qcom=
-usb-hs.c#L85
[This implementation is based on ulpi driver: https://github.com/torvalds/l=
inux/blob/master/drivers/phy/qualcomm/phy-qcom-usb-hs.c#L287C1-L287C19]=20

OR

https://github.com/torvalds/linux/blob/master/drivers/usb/chipidea/ci_hdrc_=
imx.c#L81
https://github.com/torvalds/linux/blob/master/drivers/usb/chipidea/ci_hdrc_=
imx.c#L176
https://github.com/torvalds/linux/blob/master/drivers/usb/chipidea/usbmisc_=
imx.c#L234
https://github.com/torvalds/linux/blob/master/drivers/usb/phy/phy-mxs-usb.c=
#L191
[This implementation is based on platform driver: https://github.com/torval=
ds/linux/blob/master/drivers/usb/phy/phy-mxs-usb.c#L848]

Note:
Above examples are to show the interface between the Chipidea Controller an=
d PHY.

Are these possibilities aligning with your inputs?

Regards,
Piyush Mehta