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[209.85.128.179]) by smtp.gmail.com with ESMTPSA id x7-20020a5b0287000000b00d7b9fab78bfsm1011959ybl.7.2023.10.04.05.59.11 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 04 Oct 2023 05:59:11 -0700 (PDT) Received: by mail-yw1-f179.google.com with SMTP id 00721157ae682-59f6041395dso25233857b3.1; Wed, 04 Oct 2023 05:59:11 -0700 (PDT) X-Received: by 2002:a81:c24d:0:b0:58f:bda3:8dd with SMTP id t13-20020a81c24d000000b0058fbda308ddmr2392331ywg.32.1696424351066; Wed, 04 Oct 2023 05:59:11 -0700 (PDT) MIME-Version: 1.0 References: <20230929053915.1530607-1-claudiu.beznea@bp.renesas.com> <20230929053915.1530607-17-claudiu.beznea@bp.renesas.com> In-Reply-To: <20230929053915.1530607-17-claudiu.beznea@bp.renesas.com> From: Geert Uytterhoeven Date: Wed, 4 Oct 2023 14:58:58 +0200 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v2 16/28] pinctrl: renesas: rzg2l: adapt function number for RZ/G3S To: Claudiu Cc: mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, linus.walleij@linaro.org, gregkh@linuxfoundation.org, jirislaby@kernel.org, magnus.damm@gmail.com, catalin.marinas@arm.com, will@kernel.org, quic_bjorande@quicinc.com, konrad.dybcio@linaro.org, arnd@arndb.de, neil.armstrong@linaro.org, prabhakar.mahadev-lad.rj@bp.renesas.com, biju.das.jz@bp.renesas.com, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8BIT X-Spam-Status: No, score=-0.8 required=5.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on groat.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (groat.vger.email [0.0.0.0]); Wed, 04 Oct 2023 05:59:22 -0700 (PDT) On Fri, Sep 29, 2023 at 7:39 AM Claudiu wrote: > From: Claudiu Beznea > > On RZ/G3S PFC register allow setting 8 functions for individual ports > (function1 to function8). For function1 register need to be configured > with 0, for function8 register need to be configured with 7. > We cannot use zero based addressing when requesting functions from > different code places as documentation (RZG3S_pinfunction_List_r1.0.xlsx) > states explicitly that function0 is GPIO. > > For this add a new member to struct rzg2l_hwcfg that will keep the > offset that need to be substracted before applying a value to PFC register. > > Signed-off-by: Claudiu Beznea > Reviewed-by: Geert Uytterhoeven > --- > > Changes in v2: > - in commit description mentioned that function0 is GPIO > - collected tags Thanks, will queue in renesas-pinctrl-for-v6.7. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds