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Thread-Topic: [PATCH v1] iio: adc: aspeed: Support deglitch feature. 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: aspeedtech.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: SG2PR06MB3365.apcprd06.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: c0050666-ff44-49a0-99a6-08dbc5018580 X-MS-Exchange-CrossTenant-originalarrivaltime: 04 Oct 2023 17:44:12.7972 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 43d4aa98-e35b-4575-8939-080e90d5a249 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: itYipPRBRtQqAHa8aldh84oTmR4RjUsQmxm9c7I6jsSFE6v4AlEbamGf5jRrhZ497TI0bgCrLSwFkZqt6IG2RTNxVvBl3iXP6g3JN0VIqFc= X-MS-Exchange-Transport-CrossTenantHeadersStamped: PUZPR06MB5452 X-Spam-Status: No, score=-2.6 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Wed, 04 Oct 2023 10:44:26 -0700 (PDT) =0A= >>> > Create event sysfs for applying the deglitch condition. When=0A= >>> > in_voltageY_thresh_rising_en/in_voltageY_thresh_falling_en is set to = true,=0A= >>> > the driver will use the in_voltageY_thresh_rising_value and=0A= >>> > in_voltageY_thresh_falling_value as threshold values. If the ADC valu= e=0A= >>> > falls outside this threshold, the driver will wait for the ADC sampli= ng=0A= >>> > period and perform an additional read once to achieve the deglitching= =0A= >>> > purpose.=0A= >>> >=0A= >>> > Signed-off-by: Billy Tsai =0A= >>> > ---=0A= >>> > drivers/iio/adc/aspeed_adc.c | 193 +++++++++++++++++++++++++++++++++= +-=0A= >>> > 1 file changed, 189 insertions(+), 4 deletions(-)=0A= >>> >=0A= >>> > diff --git a/drivers/iio/adc/aspeed_adc.c b/drivers/iio/adc/aspeed_ad= c.c=0A= >>> > index 998e8bcc06e1..9e746c81d916 100644=0A= >>> > --- a/drivers/iio/adc/aspeed_adc.c=0A= >>> > +++ b/drivers/iio/adc/aspeed_adc.c=0A= >>> > @@ -95,6 +95,7 @@ struct aspeed_adc_model_data {=0A= >>> > bool wait_init_sequence;=0A= >>> > bool need_prescaler;=0A= >>> > bool bat_sense_sup;=0A= >>> > + bool require_extra_eoc;=0A= >>=0A= >>> What is "eoc"? Can we use a better name or add an explanatory comment?= =0A= >>=0A= >> Hi Andrew,=0A= >> This is the signal name for our ADC controller, it means "End Of=0A= >> Conversion".=0A= >> The appearance of this signal period indicates that the ADC value is=0A= >> valid and being updated to the register.=0A= =0A= > Okay, searching for "conversion" in the datasheet didn't turn up anything= like this. It seems I wasn't off-track with asking. If you go forward with= the patch in some manner, can you add a comment to the code documenting th= e meaning of 'eoc'?=0A= =0A= Okay, I will add the comment for the meaning of eoc.=0A= =0A= >=0A= >> > /* Register ADC clock prescaler with source specified by device = tree.=0A= >> > */=0A= >> > spin_lock_init(&data->clk_lock);=0A= >> > snprintf(clk_parent_name, ARRAY_SIZE(clk_parent_name), "%s",=0A= >> > @@ -632,7 +806,14 @@ static int aspeed_adc_probe(struct platform_devic= e=0A= >> > *pdev)=0A= >> > adc_engine_control_reg_val |=3D ASPEED_ADC_CTRL_CHANNEL;=0A= >> > writel(adc_engine_control_reg_val,=0A= >> > data->base + ASPEED_REG_ENGINE_CONTROL);=0A= >> > -=0A= >> > + adc_engine_control_reg_val =3D=0A= >> > + FIELD_GET(ASPEED_ADC_CTRL_CHANNEL,=0A= >> > + readl(data->base + ASPEED_REG_ENGINE_CONTROL))= ;=0A= >> > + data->required_eoc_num =3D hweight_long(adc_engine_control_reg_v= al);=0A= >> > + if (data->model_data->require_extra_eoc &&=0A= >> > + (adc_engine_control_reg_val &=0A= >> > + BIT(data->model_data->num_channels - 1)))=0A= >> > + data->required_eoc_num +=3D 12;=0A= >=0A= >> Why 12? Why add a value to the number of engines enabled? Have I misunde= rstood?=0A= >=0A= > This behavior is specified by the hardware. In our ADC, it requires 12=0A= > dummy sampling=0A= > periods to switch the sampling channel from CH7 to CH0. Hence, this=0A= > condition checks=0A= > the enable status of channel 7 to determine the necessary delay period=0A= > for obtaining the=0A= > updated ADC values for each channel.=0A= =0A= > Okay, I feel using a magic value '12' with what you wrote above as an exp= lanation is asking a bit much of the reader. Again, if you go forward with = this patch in some fashion, can you document the meaning of 12 in a comment= (and possibly use a macro to name it)?=0A= =0A= Okay, I will include comments and use meaningful macro to name it.=0A= =0A= Thanks=