Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.36 as permitted sender) client-ip=23.128.96.36;
From:   Muhammed Efe Cetin <efectn@6tel.net>
To:     d-gole@ti.com
Cc:     conor+dt@kernel.org, devicetree@vger.kernel.org, efectn@6tel.net,
        heiko@sntech.de, jonas@kwiboo.se,
        krzysztof.kozlowski+dt@linaro.org,
        linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org,
        linux-rockchip@lists.infradead.org, megi@xff.cz,
        robh+dt@kernel.org, sebastian.reichel@collabora.com
Subject: Re: [PATCH v3 3/3] arm64: dts: rockchip: Add Orange Pi 5
Date:   Thu,  5 Oct 2023 16:54:04 +0300
Message-ID: <20231005135405.257495-1-efectn@6tel.net>
In-Reply-To: <20230928105137.5ljhuoxjc7et5thw@dhruva>
References: <20230928105137.5ljhuoxjc7et5thw@dhruva>
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Precedence: bulk

Hello,

On 28.09.2023 13:51, Dhruva Gole wrote:
> Hi,
> 
> On Aug 21, 2023 at 18:47:59 +0300, Muhammed Efe Cetin wrote:
>> Add initial support for OPi5 that includes support for USB2, PCIe2, Sata,
>> Sdmmc, SPI Flash, PMIC.
>>
>> Signed-off-by: Muhammed Efe Cetin <efectn@6tel.net>
>> Reviewed-by: Ondřej Jirman <megi@xff.cz>
>> ---
>>   arch/arm64/boot/dts/rockchip/Makefile         |   1 +
>>   .../boot/dts/rockchip/rk3588s-orangepi-5.dts  | 673 ++++++++++++++++++
>>   2 files changed, 674 insertions(+)
>>   create mode 100644 arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts
>>
> ...
> 
> Can you provide some sort of documentation on how I can build and boot
> the kernel on this board? I was unable to use the upstream arm64
> defconfig with this exact series applied to boot the board.

What was wrong when you tried to compile & boot the board? Can you provide some logs?

> 
>> +
>> +&i2c6 {
>> +	pinctrl-names = "default";
>> +	pinctrl-0 = <&i2c6m3_xfer>;
>> +	status = "okay";
>> +
>> +	hym8563: rtc@51 {
>> +		compatible = "haoyu,hym8563";
>> +		reg = <0x51>;
>> +		#clock-cells = <0>;
>> +		clock-output-names = "hym8563";
>> +		pinctrl-names = "default";
>> +		pinctrl-0 = <&hym8563_int>;
>> +		interrupt-parent = <&gpio0>;
>> +		interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>;
>> +		wakeup-source;
> 
> Are you able to actually use rtc as a wakeup source? I tried this
> on a downstream kernel that I mention below..
> 
> rtcwake -s 10 -m mem
> 
> didn't actually seem to wake the device from deepsleep after 10 seconds.
> Do you know what other pins I can use as wakeup sources?

No, i've not tried it before.

> 
>> +	};
>> +};
>> +
>> +&mdio1 {
>> +	rgmii_phy1: ethernet-phy@1 {
>> +		compatible = "ethernet-phy-ieee802.3-c22";
> 
> Just wondering, can you please give some logs of the board with eth
> working? The image that I have from opi seems to fail eth? As in I am
> not able to see any ip address. here are the logs:
> 
> https://gist.github.com/DhruvaG2000/eda2762e35013c8d5ac9f37e818103a3

Unfortunately the board is not near me currently. However, i was able to use GMAC ethernet in both the upstreram and downstream kernels. Did you try any images other than Orange Pi ones?

> 
> ...
>