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Date:   Thu, 5 Oct 2023 17:44:31 -0700
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Message-ID: <ZR9Yb25A5zOhzDol@google.com>
Subject: Re: [PATCH] KVM: x86: Ignore MSR_AMD64_BU_CFG access
From:   Sean Christopherson <seanjc@google.com>
To:     "Maciej S. Szmigiero" <mail@maciej.szmigiero.name>
Cc:     Paolo Bonzini <pbonzini@redhat.com>,
        Borislav Petkov <bp@alien8.de>, kvm@vger.kernel.org,
        x86@kernel.org, linux-kernel@vger.kernel.org,
        Tom Lendacky <thomas.lendacky@amd.com>
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On Thu, Oct 05, 2023, Maciej S. Szmigiero wrote:
> On 5.10.2023 02:10, Sean Christopherson wrote:
> > On Mon, Oct 02, 2023, Maciej S. Szmigiero wrote:
> > > On 26.09.2023 00:25, Tom Lendacky wrote:
> > > > > > It's partially documented in various AMD BKDGs, however I could=
n't find
> > > > > > any definition for this particular bit (8) - other than that it=
 is reserved.
> > > > >=20
> > > > > I found it as MSR_AMD64_BU_CFG for Model 16h, but that's Jaguar/P=
uma, not Zen1.
> > > > > My guess is that Windows is trying to write this thing:
> > > > >=20
> > > > >  =C2=A0=C2=A0 MSRC001_1023 [Table Walker Configuration] (Core::X8=
6::Msr::TW_CFG)
> > > > >  =C2=A0=C2=A0 Read-write. Reset: 0000_0000_0000_0000h.
> > > > >  =C2=A0=C2=A0 _lthree0_core[3,1]; MSRC001_1023
> > > > >=20
> > > > >  =C2=A0=C2=A0 Bits=C2=A0=C2=A0 Description
> > > > >  =C2=A0=C2=A0 63:50=C2=A0 Reserved.
> > > > >  =C2=A0=C2=A0 49=C2=A0=C2=A0=C2=A0=C2=A0 TwCfgCombineCr0Cd: combi=
ne CR0_CD for both threads of a core. Read-write. Reset: 0. Init: BIOS,1.
> > > > >  =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 1=3DThe h=
ost Cr0_Cd values from the two threads are OR'd together and used by both t=
hreads.
> > > > >  =C2=A0=C2=A0 48:0=C2=A0=C2=A0 Reserved.
> > > > >=20
> > > > > Though that still doesn't explain bit 8...=C2=A0 Perhaps a chicke=
n-bit related to yet
> > > > > another speculation bug?
> > > > >=20
> > > > > Boris or Tom, any idea what Windows is doing?=C2=A0 I doubt it ch=
anges our options in
> > > > > terms of "fixing" this in KVM, but having a somewhat accurate/hel=
pful changelog
> > > > > would be nice.
> > > >=20
> > > > It's definitely not related to a speculation bug, but I'm unsure wh=
at was
> > > > told to Microsoft that has them performing that WRMSR. The patch do=
es the
> > > > proper thing, though, as a guest shouldn't be updating that setting=
.
> > > >=20
> > > > And TW_CFG is the proper name of that MSR for Zen.
> > >=20
> > > So, should I prepare v2 with MSR_AMD64_BU_CFG -> MSR_AMD64_TW_CFG cha=
nge?
> >=20
> > If we can get Paolo's attention, I'd like to get his thoughts on puntin=
g this
> > to QEMU/userspace.  I'm worried that "handling" uarch specific MSRs in =
KVM is
> > going to paint us into a corner and force KVM to check guest F/M/S some=
day, which
> > I want to avoid at pretty much all costs.
>=20
> We already do similar ignoring in KVM for MSR_AMD64_BU_CFG2, MSR_AMD64_DC=
_CFG
> and MSR_F15H_EX_CFG, so doing this {BU_CFG2,TW_CFG} MSR filtering in QEMU=
 would
> be inconsistent with these.

Not if QEMU filters those too. :-)

The MSR filter mechanism wasn't a thing back when KVM added "support" for t=
hose
MSR, so I don't feel that punting to userspace would be inconsistent.  It's=
 more
along the lines of asking/requiring userspace to utilize a new tool to solv=
e a
problem that is best solved in userspace, with a few outliers that got
grandfathered in.

Anyways, yeah, let's get Paolo's feedback.