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From:   Victor Shih <victorshihgli@gmail.com>
Date:   Fri, 6 Oct 2023 18:30:08 +0800
Message-ID: <CAK00qKAhOnGzX8mAUADXDAjExHTQmyb5DyNkZoFht3Cn6bU1Aw@mail.gmail.com>
Subject: Re: [PATCH V1] mmc: sdhci-pci-gli: GL975[05]: Mask the replay timer
 timeout of AER
To:     Kai-Heng Feng <kai.heng.feng@canonical.com>
Cc:     ulf.hansson@linaro.org, adrian.hunter@intel.com,
        linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org,
        benchuanggli@gmail.com, HL.Liu@genesyslogic.com.tw,
        Greg.tu@genesyslogic.com.tw, kangzhen.lou@dell.com,
        Victor Shih <victor.shih@genesyslogic.com.tw>
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On Mon, Oct 2, 2023 at 10:18=E2=80=AFAM Kai-Heng Feng
<kai.heng.feng@canonical.com> wrote:
>
> Hi Victor,
>
> On Tue, Sep 26, 2023 at 4:21=E2=80=AFPM Victor Shih <victorshihgli@gmail.=
com> wrote:
> >
> > On Fri, Sep 22, 2023 at 3:11=E2=80=AFPM Kai-Heng Feng
> > <kai.heng.feng@canonical.com> wrote:
> > >
> > > Hi Victor,
> > >
> > > On Wed, Sep 20, 2023 at 4:54=E2=80=AFPM Victor Shih <victorshihgli@gm=
ail.com> wrote:
> > > >
> > > > On Tue, Sep 19, 2023 at 3:31=E2=80=AFPM Kai-Heng Feng
> > > > <kai.heng.feng@canonical.com> wrote:
> > > > >
> > > > > Hi Victor,
> > > > >
> > > > > On Tue, Sep 19, 2023 at 3:10=E2=80=AFPM Victor Shih <victorshihgl=
i@gmail.com> wrote:
> > > > > >
> > > > > > On Tue, Sep 19, 2023 at 12:24=E2=80=AFPM Kai-Heng Feng
> > > > > > <kai.heng.feng@canonical.com> wrote:
> > > > > > >
> > > > > > > Hi Victor,
> > > > > > >
> > > > > > > On Mon, Sep 18, 2023 at 6:31=E2=80=AFPM Victor Shih <victorsh=
ihgli@gmail.com> wrote:
> > > > > > > >
> > > > > > > > From: Victor Shih <victor.shih@genesyslogic.com.tw>
> > > > > > > >
> > > > > > > > Due to a flaw in the hardware design, the GL975x replay tim=
er frequently
> > > > > > > > times out when ASPM is enabled. As a result, the system wil=
l resume
> > > > > > > > immediately when it enters suspend. Therefore, the replay t=
imer
> > > > > > > > timeout must be masked.
> > > > > > >
> > > > > > > This patch solves AER error when its PCI config gets accessed=
, but the
> > > > > > > AER still happens at system suspend:
> > > > > > >
> > > > > > > [ 1100.103603] ACPI: EC: interrupt blocked
> > > > > > > [ 1100.268244] ACPI: EC: interrupt unblocked
> > > > > > > [ 1100.326960] pcieport 0000:00:1c.0: AER: Corrected error re=
ceived:
> > > > > > > 0000:00:1c.0
> > > > > > > [ 1100.326991] pcieport 0000:00:1c.0: PCIe Bus Error:
> > > > > > > severity=3DCorrected, type=3DData Link Layer, (Transmitter ID=
)
> > > > > > > [ 1100.326993] pcieport 0000:00:1c.0:   device [8086:7ab9] er=
ror
> > > > > > > status/mask=3D00001000/00002000
> > > > > > > [ 1100.326996] pcieport 0000:00:1c.0:    [12] Timeout
> > > > > > >
> > > > > > > Kai-Heng
> > > > > > >
> > > > > >
> > > > > > Hi, Kai-Heng
> > > > > >
> > > > > > Could you try applying the patch and re-testing again after res=
tarting
> > > > > > the system?
> > > > >
> > > > > Same issue happens after coldboot.
> > > > >
> > > > > > Because I applied the patch and restarted the system and it did=
n't happen.
> > > > > > The system can enter suspend normally.
> > > > > >
> > > > > > If you still have the issue after following the above instructi=
ons,
> > > > > > please provide me with your environment and I will verify it ag=
ain.
> > > > >
> > > > > The patch gets applied on top of next-20230918. Please let me kno=
w
> > > > > what else you want to know.
> > > > >
> > > > > Kai-Heng
> > > > >
> > > >
> > > > Hi, Kai-Heng
> > > >
> > > > If I want to mask the replay timer timeout AER of the upper layer r=
oot port,
> > > > could you give me some suggestions?
> > > > Or could you provide sample code for my reference?
> > >
> > > I am not aware of anyway to mask "replay timer timeout" from root por=
t.
> > > I wonder if the device supoprt D3hot? Or should it stay at D0 when
> > > ASPM L1.2 is enabled?
> > >
> > > Kai-Heng
> > >
> >
> > Hi, Kai-Heng
> >
> > Do you know any way to mask the replay timer timeout AER of the
> > upstream port from the device?
>
> Per PCIe Spec, I don't think it's possible to only mask 'replay timer tim=
eout'.
>
> > The device supports D3hot.
>
> Do you think such error plays any crucial rule? Otherwise disable
> 'correctable' errors may be plausible.
>
> Kai-Heng
>

Hi, Kai-Heng

Due to a flaw in the hardware design, the GL975x replay timer frequently
times out when ASPM is enabled.
This patch solves the AER error of the replay timer timeout for GL975x.
We have not encountered any other errors so far.
Does your 'correctable' errors mean the AER error of the replay timer timeo=
ut?
May I ask if you have any other comments on this patch?

Thanks, Victor Shih

> >
> > Thanks, Victor Shih
> >
> > > >
> > > > Thanks, Victor Shih
> > > >
> > > > > >
> > > > > > Thanks, Victor Shih
> > > > > >
> > > > > > > >
> > > > > > > > Signed-off-by: Victor Shih <victor.shih@genesyslogic.com.tw=
>
> > > > > > > > ---
> > > > > > > >  drivers/mmc/host/sdhci-pci-gli.c | 16 ++++++++++++++++
> > > > > > > >  1 file changed, 16 insertions(+)
> > > > > > > >
> > > > > > > > diff --git a/drivers/mmc/host/sdhci-pci-gli.c b/drivers/mmc=
/host/sdhci-pci-gli.c
> > > > > > > > index d83261e857a5..d8a991b349a8 100644
> > > > > > > > --- a/drivers/mmc/host/sdhci-pci-gli.c
> > > > > > > > +++ b/drivers/mmc/host/sdhci-pci-gli.c
> > > > > > > > @@ -28,6 +28,9 @@
> > > > > > > >  #define PCI_GLI_9750_PM_CTRL   0xFC
> > > > > > > >  #define   PCI_GLI_9750_PM_STATE          GENMASK(1, 0)
> > > > > > > >
> > > > > > > > +#define PCI_GLI_9750_CORRERR_MASK                         =
     0x214
> > > > > > > > +#define   PCI_GLI_9750_CORRERR_MASK_REPLAY_TIMER_TIMEOUT  =
       BIT(12)
> > > > > > > > +
> > > > > > > >  #define SDHCI_GLI_9750_CFG2          0x848
> > > > > > > >  #define   SDHCI_GLI_9750_CFG2_L1DLY    GENMASK(28, 24)
> > > > > > > >  #define   GLI_9750_CFG2_L1DLY_VALUE    0x1F
> > > > > > > > @@ -152,6 +155,9 @@
> > > > > > > >  #define PCI_GLI_9755_PM_CTRL     0xFC
> > > > > > > >  #define   PCI_GLI_9755_PM_STATE    GENMASK(1, 0)
> > > > > > > >
> > > > > > > > +#define PCI_GLI_9755_CORRERR_MASK                         =
     0x214
> > > > > > > > +#define   PCI_GLI_9755_CORRERR_MASK_REPLAY_TIMER_TIMEOUT  =
       BIT(12)
> > > > > > > > +
> > > > > > > >  #define SDHCI_GLI_9767_GM_BURST_SIZE                   0x5=
10
> > > > > > > >  #define   SDHCI_GLI_9767_GM_BURST_SIZE_AXI_ALWAYS_SET    B=
IT(8)
> > > > > > > >
> > > > > > > > @@ -561,6 +567,11 @@ static void gl9750_hw_setting(struct s=
dhci_host *host)
> > > > > > > >         value &=3D ~PCI_GLI_9750_PM_STATE;
> > > > > > > >         pci_write_config_dword(pdev, PCI_GLI_9750_PM_CTRL, =
value);
> > > > > > > >
> > > > > > > > +       /* mask the replay timer timeout of AER */
> > > > > > > > +       pci_read_config_dword(pdev, PCI_GLI_9750_CORRERR_MA=
SK, &value);
> > > > > > > > +       value |=3D PCI_GLI_9750_CORRERR_MASK_REPLAY_TIMER_T=
IMEOUT;
> > > > > > > > +       pci_write_config_dword(pdev, PCI_GLI_9750_CORRERR_M=
ASK, value);
> > > > > > > > +
> > > > > > > >         gl9750_wt_off(host);
> > > > > > > >  }
> > > > > > > >
> > > > > > > > @@ -770,6 +781,11 @@ static void gl9755_hw_setting(struct s=
dhci_pci_slot *slot)
> > > > > > > >         value &=3D ~PCI_GLI_9755_PM_STATE;
> > > > > > > >         pci_write_config_dword(pdev, PCI_GLI_9755_PM_CTRL, =
value);
> > > > > > > >
> > > > > > > > +       /* mask the replay timer timeout of AER */
> > > > > > > > +       pci_read_config_dword(pdev, PCI_GLI_9755_CORRERR_MA=
SK, &value);
> > > > > > > > +       value |=3D PCI_GLI_9755_CORRERR_MASK_REPLAY_TIMER_T=
IMEOUT;
> > > > > > > > +       pci_write_config_dword(pdev, PCI_GLI_9755_CORRERR_M=
ASK, value);
> > > > > > > > +
> > > > > > > >         gl9755_wt_off(pdev);
> > > > > > > >  }
> > > > > > > >
> > > > > > > > --
> > > > > > > > 2.25.1
> > > > > > > >