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From:   Mike Leach <mike.leach@linaro.org>
Date:   Fri, 6 Oct 2023 12:03:17 +0100
Message-ID: <CAJ9a7VhzARGmywQFPNCZ27D5UKEEPSR9_hmL5fo3daFWpB26Vg@mail.gmail.com>
Subject: Re: [PATCH 1/7] dt-bindings: arm: coresight-tmc: Add "memory-region" property
To:     Linu Cherian <lcherian@marvell.com>
Cc:     suzuki.poulose@arm.com, james.clark@arm.com, leo.yan@linaro.org,
        linux-arm-kernel@lists.infradead.org, coresight@lists.linaro.org,
        linux-kernel@vger.kernel.org, robh+dt@kernel.org,
        krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org,
        devicetree@vger.kernel.org, sgoutham@marvell.com,
        gcherian@marvell.com
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Hi Linu

On Fri, 29 Sept 2023 at 14:38, Linu Cherian <lcherian@marvell.com> wrote:
>
> memory-region 0: Reserved trace buffer memory
>
>   TMC ETR: When available, use this reserved memory region for
>   trace data capture. Same region is used for trace data
>   retention after a panic or watchdog reset.
>
>   TMC ETF: When available, use this reserved memory region for
>   trace data retention synced from internal SRAM after a panic or
>   watchdog reset.
>
> memory-region 1: Reserved meta data memory
>
>   TMC ETR, ETF: When available, use this memory for register
>   snapshot retention synced from hardware registers after a panic
>   or watchdog reset.
>
> Signed-off-by: Linu Cherian <lcherian@marvell.com>
> ---
>  .../bindings/arm/arm,coresight-tmc.yaml       | 19 +++++++++++++++++++
>  1 file changed, 19 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml b/Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml
> index cb8dceaca70e..45ca4d02d73e 100644
> --- a/Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml
> +++ b/Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml
> @@ -101,6 +101,22 @@ properties:
>            and ETF configurations.
>          $ref: /schemas/graph.yaml#/properties/port
>
> +  memory-region:
> +    items:
> +      - description: Reserved trace buffer memory for ETR and ETF sinks.
> +          For ETR, this reserved memory region is used for trace data capture.
> +          Same region is used for trace data retention as well after a panic
> +          or watchdog reset.
> +          For ETF, this reserved memory region is used for retention of trace
> +          data synced from internal SRAM after a panic or watchdog reset.
> +

Is there a valid use case for ETR where we use these areas when there
is not a panic/reset situation?

Either way - the description should perhaps mention that these areas
are only used if specifically selected by the driver - the default
memory usage models for ETR / perf are otherwise unaltered.

> +      - description: Reserved meta data memory. Used for ETR and ETF sinks.
> +
> +  memory-region-names:
> +    items:
> +      - const: trace-mem
> +      - const: metadata-mem
> +

Is there a constraint required here? If we are using the memory area
for trace in a panic situation, then we must have the meta data memory
area defined?
Perhaps a set of names such as "etr-trace-mem", "panic-trace-mem" ,
"panic-metadata-mem", were the first is for general ETR trace in
non-panic situation and then constrain the "panic-" areas to appear
together.
The "etr-trace-mem", "panic-trace-mem" could easily point to the same area.

>  required:
>    - compatible
>    - reg
> @@ -115,6 +131,9 @@ examples:
>      etr@20070000 {
>          compatible = "arm,coresight-tmc", "arm,primecell";
>          reg = <0x20070000 0x1000>;
> +        memory-region = <&etr_trace_mem_reserved>,
> +                       <&etr_mdata_mem_reserved>;
> +        memory-region-names = "trace-mem", "metadata-mem";
>
>          clocks = <&oscclk6a>;
>          clock-names = "apb_pclk";
> --
> 2.34.1
>


-- 
Mike Leach
Principal Engineer, ARM Ltd.
Manchester Design Centre. UK