Received: by 2002:a05:7412:da14:b0:e2:908c:2ebd with SMTP id fe20csp384777rdb; Fri, 6 Oct 2023 06:33:32 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFj0S/Ne6kTj6wNRm2lv/GUFiyB5t7ZExfh65Q9DwiuGOWGdir0TesnTs4lKhEaEr51Q+X5 X-Received: by 2002:a05:6a00:1592:b0:68f:cf6f:e212 with SMTP id u18-20020a056a00159200b0068fcf6fe212mr8338530pfk.20.1696599211626; Fri, 06 Oct 2023 06:33:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1696599211; cv=none; d=google.com; s=arc-20160816; b=z2ZP0DDDgNcllTIl+jvR2lJ8Sm5YkPD7fV1dWuDkV+y/Y4dMCU3i1Y2MICpfWitY4f QrdclhQxiE7C15IXUHR+ZX9UUhqW8tHYkxCodRibL+LcuLv7wk/Y7P+9AcDMQYMye9mV lks10NHZxBUjyA1MIrjvwpxlWZ/QgcZW807loy4VjDJgXDfsNkYYrTDfiXMCMW+qB2oa muEBoZ137cgTSb80mvGc9bj4WDZg4nLSN1UKWkt8toXu3Q2ZAk3DvpxkwKeL6iqHOd8W 3GLKgXq37fO8Elbqq9aDwgQkbpFJtG6X/DoHn5wdQmO8gSe9Z+0qqq4hRL+6pYMeIvRT zr0A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:in-reply-to:from :content-language:references:cc:to:subject:user-agent:mime-version :date:message-id:dkim-signature; bh=qLF3FmUojqF6i31/VFtA/YxgmVJsIVWsss0oZC+5hPk=; fh=10nPb+rxtC90e+ompWiia9JfnPLWb6MR6Ufb5oi62i4=; b=s0abVwUV3Ht/HjNRIi33/1khO4Ihj35fEHSbYnMXwOIfM2EBTDbVj3nUDJ+IRbZVDv iVNrHXv8efDHqTrsIjrOmqzQaT0cd8b0LOAYV6SRZTwqa9ssd73V05OrHhw2BKUNdEut 6ydc5DhORxEzWYIm6zKbvetlvUaZCvvFThNkLwL+AQMZVulXBOy2MIen48cL0SyNCLJP kDZbTVjaIFDOHqST5Tc4NevhCLMiXsTfRm7vf3sSiu3HjyrCoEwWcFY62WsSSNq58m+i yIOZxkVgFTRf708+ETLiz0I8bG7ZtStkKHjL2c/6wSLh9YEOKwXIx6a5TziHBoc6dlBH ZkBA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=flsaN+G1; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:3 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lipwig.vger.email (lipwig.vger.email. [2620:137:e000::3:3]) by mx.google.com with ESMTPS id m3-20020a655303000000b00565ecee8793si3538374pgq.875.2023.10.06.06.33.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 Oct 2023 06:33:31 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:3 as permitted sender) client-ip=2620:137:e000::3:3; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=flsaN+G1; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:3 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by lipwig.vger.email (Postfix) with ESMTP id 1E87B802460E; Fri, 6 Oct 2023 06:33:29 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at lipwig.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232412AbjJFNdW (ORCPT + 99 others); Fri, 6 Oct 2023 09:33:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53430 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232349AbjJFNdV (ORCPT ); Fri, 6 Oct 2023 09:33:21 -0400 Received: from mail-ej1-x62c.google.com (mail-ej1-x62c.google.com [IPv6:2a00:1450:4864:20::62c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1CB7DBB for ; Fri, 6 Oct 2023 06:33:20 -0700 (PDT) Received: by mail-ej1-x62c.google.com with SMTP id a640c23a62f3a-9b27bc8b65eso365891966b.0 for ; Fri, 06 Oct 2023 06:33:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1696599198; x=1697203998; darn=vger.kernel.org; h=content-transfer-encoding:in-reply-to:from:content-language :references:cc:to:subject:user-agent:mime-version:date:message-id :from:to:cc:subject:date:message-id:reply-to; bh=qLF3FmUojqF6i31/VFtA/YxgmVJsIVWsss0oZC+5hPk=; b=flsaN+G1a9PjHs4S4W9XHACV55W39puUtNuQuarATRVi0JJiA+W3miXMPZ+Tn+KMkZ 2PFx3WX7oGWfaohq2tUgVXqG/d0ZL8pE2bUdWOORJ7D9y8tNWB4emclVIZJnHnk4piLk m9GbHEUwsa8jatmney468/HRkoizeZpnsH9RiyQV18FxTncyjIYLA8vtNtdqAe/CjcdD CV+tGskUXkSNrEb0V5lLVoxnmzm72RxPLQl+pnwk2r6feBYLaYov7v/o2LiT/UPmprcL 8a6quGRqxXNtTt76cNM+0DgMA6gJ+97O8BkB07417jCFDCsN/N6joI3dsStNY9sHsGWT u/7A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1696599198; x=1697203998; h=content-transfer-encoding:in-reply-to:from:content-language :references:cc:to:subject:user-agent:mime-version:date:message-id :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=qLF3FmUojqF6i31/VFtA/YxgmVJsIVWsss0oZC+5hPk=; b=d6U97GLod24dGkU6wUAsE4n7etpDKKedfO+cubcAR4QldrqUD9V+BvhNrQLra61++D ylPXbVG5EwoX2Ao95wpxt1nQq+r6up+8WoDe8TtKxetM5JVyuemTzmNYDkJkwR6NYwtb 8Mg36ZhQQJDCLay/qqCG6iF9NiLQHpy4v7i9ZRYSANbpTN963sONFRm9mpgldaZl5HJ7 E4SYMY6ivyc+s6Abk3/fJJijuUK0Ep9kRm73ivTwo0bZ1jPoB1ZXChu3gvrXPggyOG9x 7ZqYVL/u9mZpTPYfpVIzsxFnb1envCtLqhp15tS1VCCnmL1/ss+TwLtk28mlSo1uPv0K veOg== X-Gm-Message-State: AOJu0YyPx0tWH7dbHYqB4X/4HaUh74kyCjMo66Ce2jvmD5Gwc5kIXTLK OyGJdp+/oxomg+EUYztDnSOtKg== X-Received: by 2002:a17:907:c241:b0:9a1:6318:4d39 with SMTP id tj1-20020a170907c24100b009a163184d39mr6842293ejc.29.1696599198565; Fri, 06 Oct 2023 06:33:18 -0700 (PDT) Received: from [192.168.2.107] ([79.115.63.123]) by smtp.gmail.com with ESMTPSA id i11-20020a170906a28b00b009737b8d47b6sm2858073ejz.203.2023.10.06.06.33.16 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 06 Oct 2023 06:33:17 -0700 (PDT) Message-ID: Date: Fri, 6 Oct 2023 14:33:11 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2] mtd: micron-st: enable lock/unlock for mt25qu512a To: SHUKLA Mamta Ramendra , "pratyush@kernel.org" , "michael@walle.cc" , "miquel.raynal@bootlin.com" , "richard@nod.at" , "vigneshr@ti.com" , "linux-mtd@lists.infradead.org" , "linux-kernel@vger.kernel.org" Cc: GEO-CHHER-bsp-development References: <20230705154942.3936658-1-mamta.shukla@leica-geosystems.com> <19800e51-a871-be9f-9eb5-5829237e2613@linaro.org> <084ed945-7674-280f-5866-9238473a294d@leica-geosystems.com> <17989610-d069-40e2-9b4d-7ca6bdf2497e@linaro.org> <2d7271b3-dd60-44bb-9700-f6a5295ea873@linaro.org> <372046cb-9135-9a6c-fdb7-307a42f55b30@leica-geosystems.com> Content-Language: en-US From: Tudor Ambarus In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Spam-Status: No, score=2.7 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, RCVD_IN_SBL_CSS,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lipwig.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (lipwig.vger.email [0.0.0.0]); Fri, 06 Oct 2023 06:33:29 -0700 (PDT) X-Spam-Level: ** Hi, Thanks for the debugging info. On 10/6/23 11:30, SHUKLA Mamta Ramendra wrote: cut > -------------------------------------------------------- > > IMO, HAS_16BIT_SR flag is causing lock/unlock failure, > since BP bits are calculated wrong then. > > I tested also for a case where I don't parse SFDP and > reverted the condition in micron_st_nor_default_init() > for 16BIT Status Register Flag. And lock/unlock fails with > same log as Non-working case. > > And this mt25qu512 has 8-BIT SR as typical micron-st flash. > Indeed, the problem is that HAS_16BIT_SR gets set when it shouldn't have to. This means that the BFPT table of the flash is wrong and we should fix the parsed settings via a post_bfpt hook. Does the following fix your problem? diff --git a/drivers/mtd/spi-nor/micron-st.c b/drivers/mtd/spi-nor/micron-st.c index 4afcfc57c896..733bbddc6829 100644 --- a/drivers/mtd/spi-nor/micron-st.c +++ b/drivers/mtd/spi-nor/micron-st.c @@ -180,6 +180,17 @@ static const struct flash_info micron_nor_parts[] = { }, }; +static int mt25qu512a_post_bfpt_fixup(struct spi_nor *nor, + const struct sfdp_parameter_header *bfpt_header, + const struct sfdp_bfpt *bfpt) +{ + nor->flags &= ~SNOR_F_HAS_16BIT_SR; +} + +static struct spi_nor_fixups mt25qu512a_fixups = { + .post_bfpt = mt25qu512a_post_bfpt_fixup, +} + static const struct flash_info st_nor_parts[] = { { .name = "m25p05-nonjedec", @@ -405,10 +416,10 @@ static const struct flash_info st_nor_parts[] = { }, { .id = SNOR_ID(0x20, 0xbb, 0x20, 0x10, 0x44, 0x00), .name = "mt25qu512a", - .size = SZ_64M, - .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ, - .fixup_flags = SPI_NOR_4B_OPCODES, + .flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_4BIT_BP | + SPI_NOR_BP3_SR_BIT6, .mfr_flags = USE_FSR, + .fixups = &mt25qu512a_fixups, }, { .id = SNOR_ID(0x20, 0xbb, 0x20), .name = "n25q512a", If yes, please add some prints in sfdp.c to determine where it's set, either in BFPT_DWORD15_QER_SR2_BIT1 or BFPT_DWORD15_QER_SR2_BIT1_NO_RD Is the datasheet for this flash public? Would you send me a link to it please? Cheers, ta