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Message-ID: <bc76767e-00c1-47ca-9a27-2aa7d2a262f6@linaro.org>
Date:   Fri, 6 Oct 2023 14:46:49 +0100
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Subject: Re: [PATCH v2] mtd: micron-st: enable lock/unlock for mt25qu512a
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From:   Tudor Ambarus <tudor.ambarus@linaro.org>
To:     SHUKLA Mamta Ramendra <mamta.shukla@leica-geosystems.com>,
        "pratyush@kernel.org" <pratyush@kernel.org>,
        "michael@walle.cc" <michael@walle.cc>,
        "miquel.raynal@bootlin.com" <miquel.raynal@bootlin.com>,
        "richard@nod.at" <richard@nod.at>,
        "vigneshr@ti.com" <vigneshr@ti.com>,
        "linux-mtd@lists.infradead.org" <linux-mtd@lists.infradead.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Cc:     GEO-CHHER-bsp-development 
        <bsp-development.geo@leica-geosystems.com>
References: <20230705154942.3936658-1-mamta.shukla@leica-geosystems.com>
 <19800e51-a871-be9f-9eb5-5829237e2613@linaro.org>
 <a8271289-0611-4e37-cf37-0be19a85656b@leica-geosystems.com>
 <084ed945-7674-280f-5866-9238473a294d@leica-geosystems.com>
 <17989610-d069-40e2-9b4d-7ca6bdf2497e@linaro.org>
 <a24d7b3b-4077-9dbe-49ae-96f595b42223@leica-geosystems.com>
 <2d7271b3-dd60-44bb-9700-f6a5295ea873@linaro.org>
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 <eb2a9138-a76e-4b1e-e001-315149c4dabd@leica-geosystems.com>
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On 10/6/23 14:33, Tudor Ambarus wrote:
> 
> Hi,
> 
> Thanks for the debugging info.
> 
> On 10/6/23 11:30, SHUKLA Mamta Ramendra wrote:
> 
> cut
> 
>> --------------------------------------------------------
>>
>> IMO, HAS_16BIT_SR flag is causing lock/unlock failure,
>> since BP bits are calculated wrong then.
>>
>> I tested also for a case where I don't parse SFDP and
>> reverted the condition in  micron_st_nor_default_init()
>> for 16BIT Status Register Flag. And lock/unlock fails with
>> same log as Non-working case.
>>
>> And this mt25qu512 has 8-BIT SR as typical micron-st flash.
>>
> 
> Indeed, the problem is that HAS_16BIT_SR gets set when it shouldn't have
> to. This means that the BFPT table of the flash is wrong and we should
> fix the parsed settings via a post_bfpt hook.
> 
> Does the following fix your problem?
> 

here it is again, this time compile tested:

diff --git a/drivers/mtd/spi-nor/micron-st.c
b/drivers/mtd/spi-nor/micron-st.c
index 4afcfc57c896..20f76e278095 100644
--- a/drivers/mtd/spi-nor/micron-st.c
+++ b/drivers/mtd/spi-nor/micron-st.c
@@ -180,6 +180,18 @@ static const struct flash_info micron_nor_parts[] = {
        },
 };

+static int mt25qu512a_post_bfpt_fixup(struct spi_nor *nor,
+                               const struct sfdp_parameter_header
*bfpt_header,
+                               const struct sfdp_bfpt *bfpt)
+{
+       nor->flags &= ~SNOR_F_HAS_16BIT_SR;
+       return 0;
+}
+
+static struct spi_nor_fixups mt25qu512a_fixups = {
+       .post_bfpt = mt25qu512a_post_bfpt_fixup,
+};
+
 static const struct flash_info st_nor_parts[] = {
        {
                .name = "m25p05-nonjedec",
@@ -405,10 +417,10 @@ static const struct flash_info st_nor_parts[] = {
        }, {
                .id = SNOR_ID(0x20, 0xbb, 0x20, 0x10, 0x44, 0x00),
                .name = "mt25qu512a",
-               .size = SZ_64M,
-               .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ |
SPI_NOR_QUAD_READ,
-               .fixup_flags = SPI_NOR_4B_OPCODES,
+               .flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB |
SPI_NOR_4BIT_BP |
+                        SPI_NOR_BP3_SR_BIT6,
                .mfr_flags = USE_FSR,
+               .fixups = &mt25qu512a_fixups,
        }, {
                .id = SNOR_ID(0x20, 0xbb, 0x20),
                .name = "n25q512a",

cut

> If yes, please add some prints in sfdp.c to determine where it's set,
> either in BFPT_DWORD15_QER_SR2_BIT1 or BFPT_DWORD15_QER_SR2_BIT1_NO_RD
> 
> Is the datasheet for this flash public? Would you send me a link to it
> please?
> 
> Cheers,
> ta