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Message-ID: <533ccc1b-7566-444e-8549-184fd272f666@intel.com>
Date:   Fri, 6 Oct 2023 10:53:52 -0700
User-Agent: Mozilla Thunderbird
Subject: Re: [PATCH v4 0/4] x86/resctrl: Non-contiguous bitmasks in Intel CAT
Content-Language: en-US
To:     Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>,
        <fenghua.yu@intel.com>, <tglx@linutronix.de>, <mingo@redhat.com>,
        <bp@alien8.de>, <dave.hansen@linux.intel.com>, <corbet@lwn.net>
CC:     <x86@kernel.org>, <hpa@zytor.com>, <linux-kernel@vger.kernel.org>,
        <linux-doc@vger.kernel.org>, <ilpo.jarvinen@linux.intel.com>
References: <cover.1696493034.git.maciej.wieczor-retman@intel.com>
From:   Reinette Chatre <reinette.chatre@intel.com>
In-Reply-To: <cover.1696493034.git.maciej.wieczor-retman@intel.com>
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Hi Maciej,

On 10/5/2023 1:14 AM, Maciej Wieczor-Retman wrote:
> Until recently Intel CPUs didn't support using non-contiguous 1s
> in Cache Allocation Technology (CAT). Writing a bitmask with
> non-contiguous 1s to the resctrl schemata file would fail.
> 
> Intel CPUs that support non-contiguous 1s can be identified through a
> CPUID leaf mentioned in the "Intel® 64 and IA-32 Architectures
> Software Developer’s Manual" document available at:
> https://www.intel.com/content/www/us/en/developer/articles/technical/intel-sdm.html
> 
> Add kernel support for detecting if non-contiguous 1s in Cache
> Allocation Technology (CAT) are supported by the hardware. Also add a
> new resctrl FS file to output this information to the userspace.
> Keep the hardcoded value for Haswell CPUs only since they do not have
> CPUID enumeration support for Cache allocation.
> 
> Since the selftests/resctrl files are going through many rewrites and
> cleanups the appropriate selftest is still a work in progress. For
> basic selftesting capabilities use the bash script attached below this
> paragraph. It checks whether various bitmasks written into resctrl FS
> generate output consistent with reported feature support.

This work conflicts with Babu's series [1] that is also ready for inclusion.
We could wait for outcome of next level review to determine who will need
to rebase. It may help to provide a snippet of the conflict resolution
in anticipation of Babu's series being merged first (I will propose exactly
the same to Babu for the scenario of this work merged first).

Reinette

[1] https://lore.kernel.org/lkml/20231003235430.1231238-1-babu.moger@amd.com/