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Date:   Sat, 7 Oct 2023 11:56:56 +0100
From:   Conor Dooley <conor@kernel.org>
To:     Randy Dunlap <rdunlap@infradead.org>
Cc:     Stephen Rothwell <sfr@canb.auug.org.au>,
        Linux Next Mailing List <linux-next@vger.kernel.org>,
        Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
        linux-riscv <linux-riscv@lists.infradead.org>,
        Paul Walmsley <paul.walmsley@sifive.com>,
        Palmer Dabbelt <palmer@dabbelt.com>,
        Albert Ou <aou@eecs.berkeley.edu>
Subject: Re: linux-next: Tree for Oct 6 (riscv: andes)
Message-ID: <20231007-poach-refute-b84fe5b7431a@spud>
References: <20231006153809.2054a0f8@canb.auug.org.au>
 <09a6b0f0-76a1-45e3-ab52-329c47393d1d@infradead.org>
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On Fri, Oct 06, 2023 at 05:28:27PM -0700, Randy Dunlap wrote:
>=20
>=20
> On 10/5/23 21:38, Stephen Rothwell wrote:
> > Hi all,
> >=20
> > Changes since 20231005:
> >=20
>=20
> on riscv 64bit:
>=20
> WARNING: unmet direct dependencies detected for ERRATA_ANDES
>   Depends on [n]: RISCV_ALTERNATIVE [=3Dn] && RISCV_SBI [=3Dy]
>   Selected by [y]:
>   - ARCH_R9A07G043 [=3Dy] && SOC_RENESAS [=3Dy] && RISCV [=3Dy] && NONPOR=
TABLE [=3Dy] && RISCV_SBI [=3Dy]
>=20
> ../arch/riscv/errata/andes/errata.c:59:54: warning: 'struct alt_entry' de=
clared inside parameter list will not be visible outside of this definition=
 or declaration
>    59 | void __init_or_module andes_errata_patch_func(struct alt_entry *b=
egin, struct alt_entry *end,
>       |                                                      ^~~~~~~~~
>=20
>=20
> Full randconfig file is attached.

Riiight. XIP_KERNEL is enabled, which means no alternatives are
permitted, but that R9A config option selects the Andes errata, which in
turn depends on alternatives.

I suppose we could do something like (untested):
diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig
index 7b74de732718..6fe85255e2ce 100644
--- a/drivers/soc/renesas/Kconfig
+++ b/drivers/soc/renesas/Kconfig
@@ -343,7 +343,7 @@ config ARCH_R9A07G043
        select ARCH_RZG2L
        select AX45MP_L2_CACHE if RISCV_DMA_NONCOHERENT
        select DMA_GLOBAL_POOL
-       select ERRATA_ANDES if RISCV_SBI
+       select ERRATA_ANDES if (RISCV_SBI & RISCV_ALTERNATIVE)
        select ERRATA_ANDES_CMO if ERRATA_ANDES
        help
          This enables support for the Renesas RZ/Five SoC.

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