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Mon, 09 Oct 2023 04:01:10 +0000 Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 399419Zh014243 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 9 Oct 2023 04:01:09 GMT Received: from [10.239.154.73] (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.30; Sun, 8 Oct 2023 21:01:05 -0700 Message-ID: <8697d115-9aa7-2a1c-4d96-25b15adb5cca@quicinc.com> Date: Mon, 9 Oct 2023 12:01:03 +0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.15.1 Subject: Re: [RESEND PATCH v6 3/3] input: pm8xxx-vibrator: add new SPMI vibrator support Content-Language: en-US To: Dmitry Torokhov CC: Dmitry Baryshkov , , , , , , , Konrad Dybcio , , , , , , Luca Weiss References: <20230922083801.3056724-1-quic_fenglinw@quicinc.com> <20230922083801.3056724-4-quic_fenglinw@quicinc.com> <12887370-0ada-359b-8a4f-18a28495c69a@quicinc.com> From: Fenglin Wu In-Reply-To: Content-Type: text/plain; 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Sun, 08 Oct 2023 21:13:29 -0700 (PDT) On 10/1/2023 12:17 AM, Dmitry Torokhov wrote: > On Mon, Sep 25, 2023 at 10:54:45AM +0800, Fenglin Wu wrote: >> >> >> On 9/24/2023 3:07 AM, Dmitry Baryshkov wrote: >>>> + >>>> + switch (vib->data->hw_type) { >>>> + case SSBI_VIB: >>>> mask = SSBI_VIB_DRV_LEVEL_MASK; >>>> shift = SSBI_VIB_DRV_SHIFT; >>>> + break; >>>> + case SPMI_VIB: >>>> + mask = SPMI_VIB_DRV_LEVEL_MASK; >>>> + shift = SPMI_VIB_DRV_SHIFT; >>>> + break; >>>> + case SPMI_VIB_GEN2: >>>> + mask = SPMI_VIB_GEN2_DRV_MASK; >>>> + shift = SPMI_VIB_GEN2_DRV_SHIFT; >>>> + break; >>>> + default: >>>> + return -EINVAL; >>> Could you please move the switch to the previous patch? Then it would >>> be more obvious that you are just adding the SPMI_VIB_GEN2 here. >>> >>> Other than that LGTM. >> >> Sure, I can move the switch to the previous refactoring patch. > > Actually, the idea of having a const "reg" or "chip", etc. structure is > to avoid this kind of runtime checks based on hardware type and instead > use common computation. I believe you need to move mask and shift into > the chip-specific structure and avoid defining hw_type. > Actually, the main motivation for adding 'hw_type' is to avoid reading 'reg_base' from DT for SSBI_VIB. It can also help to simplify the 'pm8xxx_vib_data' structure and make following code logic more straightforward and easier to understand(check hw_type instead of checking specific constant reg/mask value), it has been used in following places: 1) Avoid reading 'reg_base' from DT for SSBI_VIB. 2) Only do manual-mode-mask-write for SSBI_VIB. Previously, it was achieved by giving a valid 'drv_en_manual_mask' value only for SSBI_VIB, having hw_type make it more straightforward. 3) Not writing VIB_EN register for SSBI_VIB. A similar strategy was used previously, only write VIB_EN register when 'enable_mask' is valid, checking hw_type make it more straightforward. 4) To achieve different drive step size for SPMI_VIB (100mV per step) and SPMI_VIB_GEN2 (1mV per step). 5) Do different VIB_DRV mask and shift assignment for SPMI_VIB and SPMI_VIB_GEN2 6) Only write VIB_DRV2 for SPMI_VIB_GEN2. > Thanks. >