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Message-ID: <c5efd5a6-561c-49a8-b1ee-82997192b030@samsung.com>
Date:   Mon, 9 Oct 2023 11:52:28 +0200
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From:   Marek Szyprowski <m.szyprowski@samsung.com>
Subject: Re: [PATCH 0/4] Fix Samsung pinctrl driver static allocation of
 GPIO base warning
To:     Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>,
        Sam Protsenko <semen.protsenko@linaro.org>
Cc:     Mateusz Majewski <m.majewski2@samsung.com>,
        linux-arm-kernel@lists.infradead.org,
        linux-samsung-soc@vger.kernel.org, linux-gpio@vger.kernel.org,
        linux-kernel@vger.kernel.org, Tomasz Figa <tomasz.figa@gmail.com>,
        Sylwester Nawrocki <s.nawrocki@samsung.com>,
        Alim Akhtar <alim.akhtar@samsung.com>,
        Linus Walleij <linus.walleij@linaro.org>
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On 09.10.2023 11:42, Krzysztof Kozlowski wrote:
> On 08/10/2023 20:45, Sam Protsenko wrote:
>>>> Thank you for handling this! Those deprecation warnings have been
>>>> bugging me for some time :) While testing this series on my E850-96
>>>> board (Exynos850 based), I noticed some changes in
>>>> /sys/kernel/debug/gpio file, like these:
>>>>
>>>> 8<------------------------------------------------------------------------------------------>8
>>>> -gpiochip0: GPIOs 0-7, parent: platform/11850000.pinctrl, gpa0:
>>>> - gpio-7   (                    |Volume Up           ) in  hi IRQ ACTIVE LOW
>>>> +gpiochip0: GPIOs 512-519, parent: platform/11850000.pinctrl, gpa0:
>>>> + gpio-519 (                    |Volume Up           ) in  hi IRQ ACTIVE LOW
>>>>
>>>> -gpiochip1: GPIOs 8-15, parent: platform/11850000.pinctrl, gpa1:
>>>> - gpio-8   (                    |Volume Down         ) in  hi IRQ ACTIVE LOW
>>>> +gpiochip1: GPIOs 520-527, parent: platform/11850000.pinctrl, gpa1:
>>>> + gpio-520 (                    |Volume Down         ) in  hi IRQ ACTIVE LOW
>>>>
>>>> -gpiochip2: GPIOs 16-23, parent: platform/11850000.pinctrl, gpa2:
>>>> +gpiochip2: GPIOs 528-535, parent: platform/11850000.pinctrl, gpa2:
>>>>
>>>> ...
>>>> 8<------------------------------------------------------------------------------------------>8
>>>>
>>>> So basically it looks like all line numbers were offset by 512. Can
>>>> you please comment on this? Is it an intentional change, and why it's
>>>> happening?
>>>>
>>>> Despite of that change, everything seems to be working fine. But I
>>>> kinda liked the numeration starting from 0 better :)
>>> Could it be the reason of dynamic allocation?
>>>
>> I just asked because I didn't know :) But ok, if you want me to do
>> some digging... It seems like having GPIO_DYNAMIC_BASE=512 is not
>> necessarily the reason of dynamic allocation, but instead just a way
>> to keep 0-512 range for legacy GPIO drivers which might use that area
>> to allocate GPIO numbers statically. It's mentioned here:
>>
>>      /*
>>       * At the end we want all GPIOs to be dynamically allocated from 0.
>>       * However, some legacy drivers still perform fixed allocation.
>>       * Until they are all fixed, leave 0-512 space for them.
>>       */
>>      #define GPIO_DYNAMIC_BASE    512
>>
>> As mentioned in another comment in gpiochip_add_data_with_key(), that
>> numberspace shouldn't matter and in the end should go away, as GPIO
>> sysfs interface is pretty much deprecated at this point, and everybody
>> should stick to GPIO descriptors.
>>
>> Anyway, now that it's clear that the base number change was intended
>> and shouldn't matter, for all patches in the series:
>>
>> Reviewed-by: Sam Protsenko<semen.protsenko@linaro.org>
>> Tested-by: Sam Protsenko<semen.protsenko@linaro.org>
> If all the GPIOs changed due to switch to dynamic allocation, aren't we
> breaking all user-space users?

This /sys based GPIO interface is deprecated, so I don't think that 
stable numbers is something that we should care.

Userspace, if still uses /sys interface, should depend on the GPIO bank 
name. I remember that the GPIO numbers varied between different kernel 
versions (also compared to the 'vendor kernels'), although I don't 
remember if this was Exynos related case or other.

Best regards
-- 
Marek Szyprowski, PhD
Samsung R&D Institute Poland