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Mon, 09 Oct 2023 19:16:11 +0000 Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 399JGBa7008944 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 9 Oct 2023 19:16:11 GMT Received: from [10.110.87.129] (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.30; Mon, 9 Oct 2023 12:16:10 -0700 Message-ID: Date: Mon, 9 Oct 2023 12:16:10 -0700 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.10.0 Subject: Re: [PATCH v5 2/2] firmware: arm_scmi: Add qcom smc/hvc transport support Content-Language: en-US To: Sudeep Holla CC: , , , , , , , , , References: <20230718160833.36397-1-quic_nkela@quicinc.com> <20231006164206.40710-1-quic_nkela@quicinc.com> <20231006164206.40710-3-quic_nkela@quicinc.com> <20231009144744.yi44ljq4llaxjsb7@bogus> <20231009152952.dww3fgh5q7fqysps@bogus> <535bbc68-74bb-21e8-0e72-8de1df9cfc99@quicinc.com> <20231009190800.ydkmmt2hgieazgfl@bogus> From: Nikunj Kela In-Reply-To: <20231009190800.ydkmmt2hgieazgfl@bogus> Content-Type: text/plain; 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Mon, 09 Oct 2023 12:16:43 -0700 (PDT) On 10/9/2023 12:08 PM, Sudeep Holla wrote: > On Mon, Oct 09, 2023 at 10:49:44AM -0700, Nikunj Kela wrote: >> On 10/9/2023 8:29 AM, Sudeep Holla wrote: >>> On Mon, Oct 09, 2023 at 07:59:08AM -0700, Nikunj Kela wrote: >>>> On 10/9/2023 7:47 AM, Sudeep Holla wrote: >>>>> On Fri, Oct 06, 2023 at 09:42:06AM -0700, Nikunj Kela wrote: >>>>>> This change adds the support for SCMI message exchange on Qualcomm >>>>>> virtual platforms. >>>>>> >>>>>> The hypervisor associates an object-id also known as capability-id >>>>>> with each smc/hvc doorbell object. The capability-id is used to >>>>>> identify the doorbell from the VM's capability namespace, similar >>>>>> to a file-descriptor. >>>>>> >>>>>> The hypervisor, in addition to the function-id, expects the capability-id >>>>>> to be passed in x1 register when SMC/HVC call is invoked. >>>>>> >>>>>> The capability-id is allocated by the hypervisor on bootup and is stored in >>>>>> the shmem region by the firmware before starting Linux. >>>>>> >>>>> Since you are happy to move to signed value, I assume you are happy to loose >>>>> upper half of the range values ? >>>>> >>>>> Anyways after Bjorn pointed out inconsistency, I am thinking of moving >>>>> all the values to unsigned long to work with both 32bit and 64bit. >>>>> >>>>> Does the below delta on top of this patch works for you and makes sense? >>>> This looks good to me. Will do some testing and float v6 with the changes >>>> you suggested below. Thanks >>>> >>> Please refer or use the patch from [1] when reposting. I rebased on my >>> patch[2] that I posted few minutes back. I am trying to finalise the branch >>> and send PR in next couple of days, so please test and post sooner. Sorry >>> for the rush. >> Validated the patch from [1] below on Qualcomm ARM64 virtual platform using >> SMC64 convention. Thanks! >> > Thanks, since I have patched a bit, it is better if you post them so that > we have a link for the exact patch on the list. Just pick up the patches > from the branch[1] and post them as v6 with a change log so that all the > details are captured for reference purposes. v6 on its way, thanks! >