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Tue, 10 Oct 2023 01:42:36 -0700 (PDT) X-Spam-Level: ** > From: ankita@nvidia.com > Sent: Sunday, October 8, 2023 4:23 AM >=20 > PCI BAR are aligned to the power-of-2, but the actual memory on the > device may not. A read or write access to the physical address from the > last device PFN up to the next power-of-2 aligned physical address > results in reading ~0 and dropped writes. >=20 my question to v10 was not answered. posted again: -- Though the variant driver emulates the access to the offset beyond the available memory size, how does the userspace driver or the guest learn to know the actual size and avoid using the invalid hole to hold valid data?